MRAM device with tunnel barrier overhang

A semiconductor device comprising:

• a magnetic tunnel junction (MTJ) stack, wherein a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, wherein the tunneling barrier comprises a center portion and two outer portions, wherein the center portion is on an upper horizontal portion of the reference layer;
• and
• a first encapsulation layer located around the reference layer, wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer, wherein the first encapsulation layer has a slanted upper surface.

A method comprising:

• forming a magnetic tunnel junction (MTJ) stack, wherein a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack;
• and
• forming an encapsulation layer located around the reference layer, wherein the encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the encapsulation layer, wherein the first encapsulation layer has a slanted upper surface.