Array substrate and method for manufacturing the same
AssigneeGuangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorYi Zhang
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Abstract
An array substrate includes a substrate, a gate layer, a source-drain layer, a first passivation layer, a common electrode layer, a second passivation layer, a pixel electrode layer, and a via hole penetrating at least the second passivation layer. The via hole has a deep hole region and a shallow hole region. A first part of the via hole in the deep hole region penetrates the second passivation layer and the first passivation layer, and a second part of the via hole in the shallow hole region penetrates the second passivation layer. In the deep hole region, a pixel electrode is connected to a drain, and in the shallow hole region, the common electrode layer is electrically connected to a compensation electrode through a first connection electrode and a second connection electrode.
Claims16
An array substrate, comprising:
- a substrate;
- a gate layer provided on the substrate, the gate layer comprising a gate and a compensation electrode;
- a source-drain layer provided on a side of the gate layer away from the substrate, the source-drain layer comprising a source, a drain, and a first connection electrode;
- a first passivation layer provided on a side of the source-drain layer away from the substrate;
- a common electrode layer provided on a side of the first passivation layer away from the substrate;
- a second passivation layer provided on a side of the common electrode layer away from the substrate;
- a pixel electrode layer provided on a side of the second passivation layer away from the substrate, the pixel electrode layer comprising a pixel electrode and a second connection electrode;
- a via hole penetrating at least the second passivation layer and having a deep hole region and a shallow hole region;
- and
- wherein a first part of the via hole in the deep hole region penetrates the second passivation layer and the first passivation layer, and a second part of the via hole in the shallow hole region penetrates the second passivation layer;
- and
- in the deep hole region the pixel electrode is connected to the drain, and in the shallow hole region the common electrode layer is electrically connected to the compensation electrode through the first connection electrode and the second connection electrode.
Dependencies are inferred from the claim text.