Staggered pitch stacked vertical transport field-effect transistors
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Hemanth Jagannathan, Junli Wang, Albert M. Chu
Life of this patent
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Abstract
An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.
Claims19
A semiconductor structure comprising:
- a first plurality of vertical transport field-effect transistors (VTFETs) in a lower semiconductor layer;
- and
- a second plurality of VTFETs in an upper semiconductor layer, wherein:
- the second plurality of VTFETs is offset from the first plurality of VTFETs;
- a first VTFET of the first plurality of VTFETs has a first contact;
- a second VTFET of the second plurality of VTFETs has a second contact;
- a first interconnect is above both the first VTFET and the second VTFET;
- and
- each of the first contact and the second contact has a single, direct, straight, vertical connection to the first interconnect.
A semiconductor structure comprising:
- a first vertical transport field-effect transistor (VTFET) in a lower semiconductor layer, wherein the first VTFET has a first straight, vertical contact;
- and
- a second VTFET in an upper semiconductor layer, wherein:
- the second VTFET has a second straight, vertical contact;
- and
- the first VTFET is offset from the second VTFET by one-half of a contacted gate pitch of the second VTFET.
A semiconductor structure comprising:
- one or more vertical transport field-effect transistors (VTFETs) in an upper semiconductor layer, wherein the one or more VTFETs in the upper semiconductor layer are separated by one contacted gate pitch;
- and
- one or more VTFETs in a lower semiconductor layer, wherein:
- the one or more VTFETs in the lower semiconductor layer are separated by one contacted gate pitch;
- the one or more VTFETs in the lower semiconductor layer have straight, vertical contacts connecting to interconnect wiring above the one or more VTFETs in the upper semiconductor layer;
- and
- the one or more VTFETs in the upper semiconductor layer are offset from the one or more VTFETs in the lower semiconductor layer.
A semiconductor structure comprising:
- a first pair of vertical transport field-effect transistors (VTFETs) in a lower semiconductor layer;
- and
- a second pair of VTFETs in an upper semiconductor layer, wherein each of the second pair of VTFETs in the upper semiconductor layer is horizontally offset by half of a contacted gate pitch from at least one VTFET in the lower semiconductor layer, wherein:
- the first pair of VTFETs in the lower semiconductor layer are a first type of VTFET connected in parallel;
- the second pair of VTFETs in the upper semiconductor layer are a second type of VTFET connected in series;
- and
- each of the first pair of VTFETs in the lower semiconductor layer and each of the second pair of VTFETs in the upper semiconductor layer have a straight, vertical contact to an interconnect wire above the second pair of VTFETs.
A semiconductor structure comprising:
- a first pair of vertical transport field-effect transistors (VTFETs) in a lower semiconductor layer;
- and
- a second pair of VTFETs in an upper semiconductor layer, wherein each of the second pair of VTFETs in the upper semiconductor layer is horizontally offset by half of a contacted gate pitch from at least one VTFET in the lower semiconductor layer, wherein;
- the first pair of VTFETs in the lower semiconductor layer are a first type of VTFET connected in series;
- the second pair of VTFETs in the upper semiconductor layer are a second type of VTFET connected in parallel;
- and
- each of the first pair of VTFETs in the lower semiconductor layer and each of the second pair of VTFETs in the upper semiconductor layer have a straight, vertical contact to an interconnect wire above the second pair of VTFETs.
Dependencies are inferred from the claim text.