Source and drain regions for laterally adjacent gate-all-around (GAA) PMOS and NMOS

An integrated circuit structure, comprising:

• a first device comprising (i) a first source or drain region and a corresponding first source or drain contact, (ii) a first gate structure and a corresponding first gate contact, (iii) a first layer comprising a first dielectric material and an adjacent second layer comprising a second dielectric material, wherein the first layer and the second layer are laterally between the first gate contact and the first source or drain contact, and (iv) a first inner spacer laterally between the first source or drain region and the first gate structure, wherein the first inner spacer is aligned below the first layer and is not aligned below the second layer;
• and
• a second device comprising (i) a second source or drain region and a corresponding second source or drain contact, (ii) a second gate structure and a corresponding second gate contact, (iii) a third layer comprising the first dielectric material and an adjacent fourth layer comprising the second dielectric material, wherein the third layer and the fourth layer are laterally between the second gate contact and the second source or drain contact, and (iv) a second inner spacer laterally between the second source or drain region and the second gate structure, wherein the second inner spacer is aligned below both the third layer and the fourth layer.

An integrated circuit structure, comprising:

• a first device comprising (i) a first source or drain region, (ii) a first body comprising semiconductor material laterally extending from the first source or drain region, (iii) a first layer comprising a first dielectric material on a sidewall of the first source or drain region, and (iv) a second layer comprising a second dielectric material on the first layer;
• and
• a second device comprising (i) a second source or drain region, (ii) a second body comprising semiconductor material laterally extending from the second source or drain region, (iii) a third layer comprising the second dielectric material on a sidewall of the second source or drain region, wherein the second device lacks the first dielectric material on the sidewall of the second source or drain region, and wherein the first layer comprises discontinuous remnants of the first dielectric material that are between the first source or drain region and the second layer.