Vertical thin film transistor with dual gate electrodes

A method of fabricating a dual gate vertical TFT, comprising:

• providing a substrate layer;
• forming a first layer stack by:
• depositing a first conductor layer on the substrate layer to form a source electrode;
• depositing a first insulator layer on the first conductor layer to form a mid-gate;
• depositing a second conductor layer on the first insulator layer to form a drain electrode;
• wherein the layers of the first layer stack are patterned to expose at least portions of the first conductor layer, the first insulator layer, and the second conductor layer;
• forming a second layer stack by:
• depositing a semiconductor layer making electrical contact with the source electrode and the drain electrode, forming a substantially vertical channel between the source electrode and the drain electrode across the mid-gate;
• depositing a second insulator layer forming a top-gate insulator on the semiconductor layer;
• depositing a third conductor layer forming a top-gate electrode on the second insulator layer;
• wherein the layers of the second layer stack are patterned to form a top-gate.