Semiconductor device and manufacturing method

A semiconductor device comprising a semiconductor body, a gate electrode and a first electrode, wherein

• the semiconductor body comprises a first region which is a source region or an emitter region, and comprises a well region located next to the first region, the first region is of a first conductivity type and the well region is of a different, second conductivity type,
• the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulator layer,
• the first region is electrically contacted by means of the first electrode which is a source electrode or an emitter electrode,
• in the first region there is at least one current limiting region,
• the at least one current limiting region is a sub-region of the first region with a decreased electrical conductivity, and
• the semiconductor device is of planar design so that the gate insulation layer and the gate electrode are applied on a planar section of a top side of the semiconductor body, the first region is located at the top side, and wherein
• either, seen in cross-section of the semiconductor body through the first region and through the gate electrode, the first region extends all around the at least one current limiting region in directions towards the well region so that the first region is embedded in the well region and so that the at least one current limiting region is embedded in the first region,
• or the at least one current limiting region is completely embedded in the first region so that, seen in cross-section of the semiconductor body, the first region is all around the at least one current limiting region.