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US 12,751,057 B2Granted
Transistor structure with gate isolation structures and method of fabricating thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTa-Chun Lin, Jhon Jhy Liaw
Life of this patent
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Abstract
Semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. The second gate isolation structure may be formed on a shallow trench isolation feature. The height of the first gate isolation structure is less than the height of the second gate isolation structure. The composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. In some implementations, the first gate isolation structure is formed concurrently with gate spacers.
Claims12
A semiconductor structure, comprising:
- a dielectric fin extending in a first direction in a top view;
- a first stack of a plurality of nanostructures disposed adjacent a first sidewall of the dielectric fin, wherein the first stack of the plurality of nanostructures includes a first channel layer and a second channel layer disposed over and spaced a vertical distance from the first channel layer in a cross-sectional view;
- a second stack of a plurality of nanostructures disposed adjacent a second sidewall of the dielectric fin, the second sidewall opposing the first sidewall, wherein the second stack of the plurality of nanostructures includes a third channel layer and a fourth channel layer disposed over and spaced a vertical distance from the third channel layer in the cross-sectional view;
- a third stack of a plurality of nanostructure channel layers spaced a lateral distance from the second stack of the plurality of nanostructures in the cross-sectional view, wherein a shallow trench isolation (STI) is between the second stack of the plurality of nanostructures and the third stack of the plurality of nanostructure channel layers;
- a first gate segment disposed over and between the first channel layer and the second channel layer of the first stack of the plurality of nanostructures, a second gate segment disposed over and between the third channel layer and the fourth channel layer of the second stack of the plurality of nanostructures, and a third gate segment disposed over and between channel layers of the third stack of the plurality of nanostructure channel layers, wherein each of the first, second and third gate segments extend in a second direction in the top view and are collinear in the second direction, the second direction perpendicular to the first direction in the top view;
- a first gate isolation feature between the first gate segment and the second gate segment, wherein the first gate isolation feature extends to interface an upper surface of the dielectric fin;
- a second gate isolation feature between the second gate segment and the third gate segment, wherein the second gate isolation feature extends to interface an upper surface of the STI;
- and
- wherein in the top view the first gate isolation feature has a first length measured at a center line of the first gate segment and a second length at a line collinear with an edge of the first gate segment, wherein the second length is at least about 1.2 times the first length.
6 more elements
A semiconductor structure, comprising:
- a dielectric fin extending vertically above a substrate and extending substantially horizontally in a top view;
- a first plurality of vertically stacked nanostructures and a second plurality of vertically stacked nanostructures in a first cross-sectional view, the first plurality and the second plurality of vertically stacked nanostructure extending substantially horizontally in a top view, the dielectric fin disposed between the first plurality of nanostructures and the second plurality of nanostructures;
- a first gate segment disposed over and between the first plurality of nanostructures;
- a second gate segment disposed over and between the second plurality of nanostructures;
- a first gate isolation feature disposed between the first gate segment and the second gate segment and on the dielectric fin, wherein the first gate isolation feature has a first sidewall having an interface with the first gate segment and the first plurality of nanostructures and has a second sidewall having an interface with the second gate segment and the second plurality of nanostructures in a cross-sectional view;
- and
- a second gate isolation feature disposed on a shallow trench isolation (STI) spaced a distance from the second plurality of nanostructures, wherein the first gate isolation feature has a different composition than the second gate isolation feature.
4 more elements
Dependencies are inferred from the claim text.