Semiconductor device including interfacial layer with CET scaling and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising:

• forming a channel portion;
• subjecting the channel portion to an oxygen plasma such that a surface portion of the channel portion is oxidized to form a first oxide film;
• forming a second oxide film on the first oxide film, the first oxide film and the second oxide film being made of different materials;
• performing a treatment such that the first oxide film and the second oxide film are formed into an interfacial layer which includes a first dielectric material and which is formed on the channel portion;
• forming a gate dielectric layer which includes a second dielectric material and which is formed on the interfacial layer, the second dielectric material being different from the first dielectric material;
• introducing dipole elements into one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage;
• and
• forming a gate electrode on the gate dielectric layer such that the gate electrode is separated from the channel portion by the interfacial layer and the gate dielectric layer.

A semiconductor device, comprising:

• a channel portion;
• an interfacial layer which is disposed on the channel portion and which includes a first dielectric material, the first dielectric material including a rare-earth metal;
• a gate dielectric layer which is disposed on the interfacial layer and which includes a second dielectric material, the second dielectric material being different from the first dielectric material;
• a barrier layer which is disposed between the interfacial layer and the gate dielectric layer, and which includes a barrier material, the barrier material having
• a conduction band edge energy that is greater than a conduction band edge energy of each of the first dielectric material and the second dielectric material, and
• a valence band edge energy that is lower than a valence band edge energy of each of the first dielectric material and the second dielectric material;
• and
• a gate electrode disposed on the gate dielectric layer such that the gate electrode is separated from the channel portion by the interfacial layer, the gate dielectric layer, and the barrier layer.