Semiconductor device comprising connections through stacked transistors for routing flexibility
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Wei Peng, Chun-Yen Lin, Wei-Cheng Tzeng, Jiann-Tyng Tzeng
Life of this patent
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Abstract
A semiconductor device includes a first transistor, a second transistor, a third transistor, and a contact. The first transistor includes a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D. The first transistor and the second transistor are stacked over the third transistor. The contact covers the second S/D of the first transistor. The contact is electrically connected to the second transistor and electrically isolated from the second S/D.
Claims20
A semiconductor device, comprising:
- a first transistor comprising a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D;
- a second transistor;
- a third transistor, wherein the first transistor and the second transistor are stacked over the third transistor;
- a first contact covering the second S/D of the first transistor, wherein the first contact is electrically connected to the second transistor and electrically isolated from the second S/D;
- and
- an isolation layer entirely covering a circumferential surface of the second S/D of the first transistor and electrically isolating the first contact from the second S/D;
- wherein the second S/D of the first transistor is laterally and vertically surrounded by the first contact with the isolation layer therebetween;
- and
- wherein the second S/D is a shared S/D between the first transistor and the second transistor.
A semiconductor device, comprising:
- a first transistor comprising a first S/D, a second S/D, and a first gate between the first S/D and the second S/D;
- a second transistor stacked directly under the first transistor and comprising a third S/D directly under the second S/D of the first transistor;
- a third transistor stacked over the second transistor;
- a conductive trace over the first transistor;
- and
- a contact covering the second S/D of the first transistor, wherein the contact is electrically connected to the conductive trace and electrically isolated from the second S/D, and the contact comprises a first extension between a bottom surface of the second S/D and a top surface of the third S/D;
- wherein the second S/D of the first transistor is laterally and vertically surrounded by the contact;
- and
- wherein the second S/D is a shared S/D between the first transistor and the third transistor.
A semiconductor device, comprising:
- a first transistor comprising a first S/D, a second S/D, and a first gate between the first S/D and the second S/D;
- a second transistor stacked directly under the first transistor;
- a third transistor stacked over the second transistor and comprising a third S/D;
- a conductive trace over the first transistor;
- and
- a first contact covering the second S/D of the first transistor, wherein the first contact is electrically isolated from the second S/D, and the first contact is electrically connected to the third S/D of the third transistor through the conductive trace;
- wherein the second S/D of the first transistor is laterally and vertically surrounded by the first contact;
- wherein the second transistor comprises a fourth S/D directly under the second S/D, the fourth S/D comprises a conductive layer and a spacer layer covering the conductive layer, the spacer layer has an opening exposing a portion of the conductive layer, and the portion of the conductive layer is protruding out of the opening of the spacer layer and extending into a recess of the first contact;
- and
- wherein the second S/D is a shared S/D between the first transistor and the third transistor.
Dependencies are inferred from the claim text.