Charge balanced power transistors

A semiconductor device, comprising:

• a semiconductor region having a plurality of alternating first and second material layers deposited on each other, the plurality of alternating first and second material layers forming a plurality of two-dimensional carrier channels of a first conductivity type, the first conductivity type being one of a n-type conductivity or a p-type conductivity, the plurality of two-dimensional carrier channels having a net charge, the semiconductor region including a first semiconductor region coupled with a drain terminal and a second semiconductor region coupled with a source terminal;
• a third semiconductor region comprising a third material of a second conductivity type, the second conductivity type being the other of the n-type conductivity or the p-type conductivity, the third semiconductor region having a gate region and a net charge region substantially perpendicular to the gate region, the gate region comprising the third material electrically coupled with a gate terminal and disposed between the first and second semiconductor regions, the third material of the gate region continuously extending through the plurality of alternating first and second material layers forming the plurality of two-dimensional carrier channels, where the plurality of alternating first and second material layers of the first and second semiconductor regions are separated on opposite sides of the third material of the gate region, and the net charge region comprising a layer of the third material coupled to and extending from the third material of the gate region, the layer of third material disposed over and substantially parallel to the plurality of alternating first and second material layers in the first semiconductor region, the net charge region having a net charge in a depletion region within the third material between the gate terminal and the drain terminal that is substantially equal to the net charge of the plurality of two-dimensional carrier channels in the first semiconductor region when the semiconductor device is in an off-state.