Dual-gate semiconductor structures for power applications

A mobile terminal with power amplifier circuitry having a dual-gate HEMT, the dual-gate HEMT comprising:

• a substrate;
• a body region over the substrate comprising:
• a source ohmic contact, a floating ohmic contact between the source ohmic contact and a drain ohmic contact;
• a barrier layer;
• a channel layer;
• and
• a buffer layer;
• wherein the barrier layer extends over the channel layer and the channel layer extends over the buffer layer;
• and
• wherein the source ohmic contact, the floating ohmic contact, and the drain ohmic contact extend into the barrier layer, the channel layer, and the buffer layer so that the barrier layer, the channel layer, and the buffer layer each have a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
• a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact;
• and
• a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

A user device with power amplifier circuitry having a dual-gate HEMT, the dual-gate HEMT comprising:

• a substrate;
• a body region over the substrate comprising:
• a source ohmic contact, a floating ohmic contact between the source ohmic contact and a drain ohmic contact;
• a barrier layer;
• a channel layer;
• and
• a buffer layer;
• wherein the barrier layer extends over the channel layer and the channel layer extends over the buffer layer;
• and
• wherein the source ohmic contact, the floating ohmic contact, and the drain ohmic contact extend into the barrier layer, the channel layer, and the buffer layer so that the barrier layer, the channel layer, and the buffer layer each have having a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
• a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact;
• and
• a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

A method of fabricating a semiconductor structure, comprising:

• providing a substrate;
• providing a body region over the substrate, wherein:
• a source ohmic contact, a drain ohmic contact, and a floating ohmic contact between the source ohmic contact and the drain ohmic contact are formed;
• forming a barrier layer;
• forming a channel layer;
• and
• forming a buffer layer;
• wherein the source ohmic contact, the floating ohmic contact, and the drain ohmic contact extend into the barrier layer, the channel layer, and the buffer layer so that the barrier layer, the channel layer, and the buffer layer each have a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
• forming a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact;
• and
• forming a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.