Field effect transistor having same gate and source doping, cell structure, and preparation method

A method for preparing a cell structure for a field effect transistor having same gate and source doping, comprising following steps:

• (a) using a silicon carbide substrate with a doping type of a first conductivity type, and providing a semiconductor epitaxial layer of the first conductivity type on a front face of the silicon carbide substrate;
• using a photolithography plate (photolithography mask) to shield a portion of a surface, and etching on the front face of the silicon carbide substrate where the semiconductor epitaxial layer is provided, a silicon carbide mesa by an etching process, with an etching depth of 0.5 to 5 μm;
• (b) performing ion implantation of a floating region by using the same photolithography mask, wherein the specific process comprises forming a floating region of a second conductivity type by at least one tilt implantation and vertical implantation of Al ions, so that bottom and side walls of a trench formed by the etching process of step (a) are uniformly implanted;
• (c) peeling off the mask layer and performing vertical N implantation to form a gate implantation region and a source implantation region, of the first conductivity type;
• (d) growing a dielectric layer on the side walls of the trench as an electrode isolation dielectric to isolate a gate from a source;
• and
• (e) depositing a metal and annealing to form an alloy on surfaces of the gate implantation region, the source implantation region, and the substrate, of the first conductivity type, respectively, as ohmic contacts, wherein the alloy contains at least one of a silicide or a carbide,
• wherein step (b) further comprises disposing a channel implantation region in the semiconductor epitaxial layer at a depth greater than a depth to which the floating region extends from a surface of the trench, wherein a doping concentration of the channel implantation region is higher than a doping concentration of a remaining portion of the semiconductor epitaxial layer, and
• wherein in plan view, the source implantation region and the floating region each comprises a substantially hexagonal outline defined by six side faces, including three front-facing faces and three back-facing faces.