Low cross-talk noise resistive memory devices on a SOI substrate and methods of making the same

A semiconductor structure comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, a buried insulating layer, and a top semiconductor layer;
• a first deep trench isolation structure comprising a first non-insulating moat structure laterally surrounding a first portion of the top semiconductor layer that is located in a first device region in a plan view, wherein the first non-insulating moat structure has a top surface located at, or below, a horizontal plane including a top surface of the top semiconductor layer;
• a second deep trench isolation structure comprising a second non-insulating moat structure laterally surrounding the first deep trench isolation structure in the plan view;
• and
• a resistive memory array located on the first portion of the top semiconductor layer, and located entirely within the first device region in the plan view.

A method of forming a semiconductor structure, the method comprising:

• forming at least one moat trench through a top semiconductor layer and a buried insulating layer of a semiconductor-on-insulator (SOI) substrate, wherein each of the at least one moat trench laterally surrounds a first portion of the top semiconductor layer that is located in a first device region in a plan view;
• forming at least one deep trench isolation structure in the at least one moat trench such that one of the at least one deep trench isolation structure comprises:
• a first inner insulating liner laterally surrounding the first portion of the top semiconductor layer;
• a first non-insulating moat structure laterally surrounding the first inner insulating liner and having a top surface located at, or below, a horizontal plane including a top surface of the top semiconductor layer;
• and
• a first outer insulating liner that laterally surrounds the first non-insulating moat structure;
• and
• forming a resistive memory array on the first portion of the top semiconductor layer, wherein the resistive memory array is formed entirely within the first device region in the plan view.