Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Tomoaki Atsumi, Yuta Endo
Life of this patent
Estimating the term…
Abstract
A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.
Claims4
A semiconductor device comprising:
- a substrate;
- and
- a memory cell string comprising a first memory cell over the substrate,
- wherein the first memory cell comprises a first transistor,
- wherein the first transistor comprises a first gate electrode, a gate insulating layer, a first oxide semiconductor layer, a source electrode, a drain electrode, and a back gate electrode,
- wherein a channel formation region of the first transistor is in the first oxide semiconductor layer,
- wherein a channel length direction of the first transistor is parallel to a first direction perpendicular to a top surface of the substrate,
- wherein a first conductor serving as the first gate electrode faces the channel formation region with the gate insulating layer therebetween,
- wherein a second conductor serving as the back gate electrode faces the channel formation, region with an insulator therebetween,
- wherein a third conductor serving as the source electrode faces a fourth conductor serving as the drain electrode with the gate insulating layer therebetween,
- wherein the third conductor is in contact with a first side surface of the first oxide semiconductor layer,
- wherein the fourth conductor is in contact with a second side surface of the first oxide semiconductor layer, and
- wherein the second conductor extends in the first direction.
A semiconductor device comprising:
- a substrate;
- a prism-like insulator over the substrate;
- and
- a memory cell string comprising a first memory cell on a first side surface of the prism-like insulator and a second memory cell on a second side surface of the prism-like insulator;
- wherein the first memory cell comprises a first transistor,
- wherein the first transistor comprises a first gate electrode, a gate insulating layer, a first oxide semiconductor layer, a source electrode, a drain electrode, and a back gate electrode,
- wherein a channel formation region of the first transistor is in the first oxide semiconductor layer,
- wherein a channel length direction of the first transistor is parallel to a first direction perpendicular to a top surface of the substrate,
- wherein a first conductor serving as the first gate electrode faces the channel formation region with the gate insulating layer therebetween,
- wherein a second conductor serving as the back gate electrode faces the channel formation region with the prism-like insulator therebetween,
- wherein a third conductor serving as the source electrode faces a fourth conductor serving as the drain electrode with the gate insulating layer therebetween,
- wherein the third conductor is in contact with a first side surface of the first oxide semiconductor layer,
- wherein the fourth conductor is in contact with a second side surface of the first oxide semiconductor layer, and
- wherein the second conductor extends in the first direction.
Dependencies are inferred from the claim text.