3D synapse device stack, 3D stackable synapse array using the 3D synapse device stacks and method of fabricating the stack

A three-dimensional synapse device stack comprising:

• a channel hole disposed on a substrate, the channel hole extending in a direction perpendicular to a surface of the substrate, having a pillar shape, and having an interior filled with an insulating material;
• a semiconductor body disposed on an outer circumferential surface of the channel hole and made of a semiconductor material;
• a plurality of first insulating layers at least partially in contact with the semiconductor body;
• a plurality of sources disposed on a first side of an outer circumferential surface of the semiconductor body and stacked alternately with the first insulating layers;
• a source line electrode electrically connected to the plurality of sources;
• a plurality of drains disposed on a second side of the outer circumferential surface of the semiconductor body, the second side being opposite to the first side and stacked alternately with the first insulating layers;
• a drain line electrode electrically connected to the plurality of drains;
• a plurality of first word lines disposed on a third side of the outer circumferential surface of the semiconductor body, the third side being positioned between the sources and the drains and stacked alternately with the first insulating layers;
• a plurality of first insulator stacks disposed between the first word lines and the semiconductor body and including at least one layer for storing charges or causing polarization;
• a plurality of second word lines disposed on a fourth side of the outer circumferential surface of the semiconductor body, the fourth side being positioned between the sources and the drains and spaced apart from the third side and stacked alternately with the first insulating layers;
• and
• a plurality of second insulator stacks disposed between the second word lines and the semiconductor body and including at least one layer for storing charges or causing polarization,
• wherein the semiconductor body, a source, a drain, a first insulator stack and a first word line located at a same level on the surface of the channel hole constitute a first synapse device, and a plurality of first synapse devices stacked along the channel hole constitute a first synapse device stack,
• wherein the semiconductor body, a source, a drain, a second insulator stack and a second word line located at a same level on the surface of the channel hole constitute a second synapse device, and a plurality of second synapse devices stacked along the channel hole constitute a second synapse device stack, and
• wherein a first synapse device and a second synapse device located at a same level share a source and a drain, and respectively include a first word line and a second word line spaced apart from each other, and each of the word lines is electrically isolated from adjacent synapse device stacks.