Semiconductor memory device and method of producing same

A method of producing a semiconductor memory device, comprising:

• providing a substrate;
• forming a stacked structure on the substrate, the stacked structure comprising a bottom-layer dielectric layer, a sacrificial layer and a top-layer dielectric layer which are superposed in sequence from bottom to top;
• forming a plurality of capacitor holes arranged at intervals in the stacked structure, each of the plurality of capacitor holes penetrating through the stacked structure and exposing the substrate;
• forming a bottom electrode layer in each of the plurality of capacitor holes, the bottom electrode layer filling up each of the plurality of capacitor holes, each bottom electrode layer having a columnar structure;
• removing the top-layer dielectric layer to expose the sacrificial layer and an upper part of each bottom electrode layers;
• forming a first capacitor dielectric layer on an exposed surface of the sacrificial layer and a top surface and sidewalls of the upper part of each bottom electrode layers;
• forming a first top electrode layer on the first capacitor dielectric layer;
• forming a plurality of openings extending from the first top electrode layer through the first capacitor dielectric layer to expose the sacrificial layer, wherein each of the plurality of openings simultaneously overlapping at least the two adjacent ones of the bottom electrode layers;
• removing the sacrificial layer through the plurality of openings to form a gap between two adjacent ones of the bottom electrode layers;
• forming a second capacitor dielectric layer having a first portion on the first top electrode layer, and a second portion on sidewalls of each of the plurality of openings and the gap, and a bottom surface of the gap;
• forming a second top electrode layer on the second capacitor dielectric layer, wherein a first portion of the second top electrode layer filling up each of the plurality of openings and the gap, and a second portion of the second top electrode layer protruding from the plurality of openings and overlying the first top electrode layer;
• removing the second portion of the second top electrode layer and the first portion of the second capacitor dielectric layer to expose the first top electrode layer;
• and
• forming an interconnection conductive layer on the first top electrode layer and the second top electrode layer, wherein the interconnection conductive layer electrically connecting the first top electrode layer to the second top electrode layer.