FPGA neighbor output mux direct connections to minimize routing hops
AssigneeEfinix, Inc.
InventorsMarcel Gort, Brett Grady
Life of this patent
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Abstract
Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.
Claims23
A field programmable gate array (FPGA) apparatus comprising:
- a plurality of logic block tiles including one or more first logic block tiles and one or more second logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles;
- and
- one or more additional connections extending from the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles, wherein the one or more second logic block tiles are neighboring logic block tiles to the one or more first logic block tiles, and wherein the one or more additional connections are added to the one or more outputs of the one or more first logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles, wherein the one or more additional connections comprise one or more third wires.
An apparatus, comprising:
- a memory;
- and
- a processor coupled to the memory, wherein the processor is configured to:
- determine routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles;
- determine routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles;
- and
- additionally connect the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles, wherein the processor is further configured to additionally connect the one or more outputs of the one or more first logic block tiles to one or more inputs of output multiplexors (muxes) of the one or more second logic block tiles using one or more third wires.
A non-transitory machine readable medium storing instructions that cause a data processing system to perform operations comprising:
- determining routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles;
- determining routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles, and
- additionally connecting the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles, wherein the instructions further cause the data processing system to perform operations comprising:
- additionally connecting the one or more outputs of the one or more first logic block tiles to one or more inputs of output muxes of the one or more second logic block tiles using one or more third wires.
Dependencies are inferred from the claim text.