Techniques to mitigate drift in bias voltages

A method, comprising:

• generating a reference current based on a reference voltage of a memory device and an offset voltage range trim;
• generating a temperature adjustment current based on a detected temperature;
• generating a supply adjustment current based on a supplied voltage and the reference voltage of the memory device;
• adjusting the reference current based on the temperature adjustment current and the supply adjustment current;
• applying the adjusted reference current to a first N-channel metal-oxide semiconductor (NMOS) transistor and a second resistance in series to form a first bias voltage;
• applying the adjusted reference current to a second NMOS transistor to form a second bias voltage;
• and
• supplying the first bias voltage and the second bias voltage to receiver circuitry of the memory device.

A memory device, comprising:

• bias voltage generation circuitry configured to:
• generate a reference current based on offset voltage range trim;
• generate an adjusted reference current based on the reference current, a temperature adjustment current, and a supply adjustment current;
• and
• apply the adjusted reference current to replica decision feedback equalizer (DFE) circuitry to form a high bias voltage and a low bias voltage;
• first circuitry configured to generate the temperature adjustment current based on a detected temperature of the memory device;
• and
• second circuitry configured to generate the supply adjustment current based on a supplied voltage, a reference voltage of the memory device, and a supply correction trim.