Interface device for multiplexing multiple network ports over single SERDES

A method for converting a plurality of input data streams into a single output data stream, the method comprising:

• distributing, by first circuitry of an interface device, bit blocks from a plurality of input data streams to a number of first data streams that is less than a number of input data streams in the plurality of input data streams;
• periodically inserting, by second circuitry, a set of alignment markers (AMs) into the first data streams in between bit blocks, the set of AMs comprising at most the number of input data streams;
• locking, by third circuitry, to AMs in the first data streams;
• after locking to the AMs and prior to providing data corresponding to the first data streams to forward error correction (FEC) encoding circuitry,
• removing, by fourth circuitry, the AMs, and
• reinserting, by the fourth circuitry, the AMs so that after being processed by the EEC encoding circuitry, the AMs are located at an FEC codeword boundary and bits of a first AM, among the set of AMs, are spread across multiple outputs streams of the FEC encoding circuitry;
• encoding, by the FEC encoding circuitry, data output by the fourth circuitry according to an FEC to generate FEC codewords;
• distributing, by the FEC encoding circuitry, data from the FEC codewords to the multiple outputs streams of the FEC encoding circuitry;
• and
• generating, by fifth circuitry, the single output data stream based on the multiple output streams of the FEC encoding circuitry.

An interface device for converting a plurality of input data streams into a single output data stream, the interface device comprising:

• first circuitry configured to:
• write data from a plurality of input streams to respective FIFO buffers at a first rate,
• read data from the FIFO buffers at a second rate higher than the first rate to generate respective first data streams,
• periodically pause reading data from the FIFO buffers,
• periodically insert dummy bit blocks and alignment markers (AMs) into the first data streams, including periodically inserting the dummy bit blocks in connection with periodically pausing the reading of data from the FIFO buffers, and
• distribute data from the first data streams to a plurality of second data streams, wherein a number second data streams is less than a number of first data streams;
• second circuitry configured to lock to the AMs in the second data streams and provide data in the second streams to forward error correction (FEC) encoder circuitry;
• the FEC encoder circuitry, the FEC encoding circuitry configured to encode data from the second circuitry according to an FEC code to generate FEC codewords;
• and
• third circuitry configured to generate the single output data stream based on the FEC codewords generated by the FEC encoding circuitry.

A method for converting a plurality of input data streams into a single output data stream, the method comprising:

• writing data from a plurality of input streams to respective first-in-first-out (FIFO) buffers at a first rate;
• reading data from the FIFO buffers at a second rate higher than the first rate to generate respective first data streams;
• periodically pausing reading data from the FIFO buffers;
• periodically inserting, by first circuitry, dummy bit blocks and alignment markers (AMs) into the first data streams, including periodically inserting the dummy bit blocks into the first data streams in connection with periodically pausing the reading of data from the FIFO buffers;
• distributing, by the first circuitry, data from the first data streams to a plurality of second data streams, wherein a number second data streams is less than a number of first data streams;
• locking, by second circuitry, to the AMs in the second data streams;
• providing, by the second circuitry, data in the second streams to forward error correction (FEC) encoder circuitry;
• encoding, by the FEC encoder circuitry, data from the second circuitry according to an FEC code to generate FEC codewords;
• and
• generating, by third circuitry, the single output data stream based on the FEC codewords generated by the FEC encoding circuitry.

An interface device for converting a plurality of input data streams into a single output data stream, the interface device comprising:

• first circuitry configured to:
• write data from a plurality of input streams to respective FIFO buffers at a data rate of 10.3125 gigabits per second (Gbps),
• read data from the FIFO buffers at a data rate of 12.375 Gbps to generate respective first data streams,
• periodically insert dummy bit blocks and alignment markers (AMs) into the first data streams, and
• distribute data from the first data streams to a plurality of second data streams, wherein a number second data streams is less than a number of first data streams;
• second circuitry configured to lock to the AMs in the second data streams and provide data in the second streams to forward error correction (FEC) encoder circuitry;
• the FEC encoder circuitry, the FEC encoding circuitry configured to encode data from the second circuitry according to an FEC code to generate FEC codewords;
• and
• third circuitry configured to generate the single output data stream based on the FEC codewords generated by the FEC encoding circuitry.

A method for converting a plurality of input data streams into a single output data stream, the method comprising:

• writing data from a plurality of input streams to respective first-in-first-out (FIFO) buffers at a data rate of 10.3125 gigabits per second (Gbps);
• reading data from the FIFO buffers at a data rate of 12.375 Gbps to generate respective first data streams;
• periodically inserting, by first circuitry, dummy bit blocks and alignment markers (AMs) into the first data streams;
• distributing, by the first circuitry, data from the first data streams to a plurality of second data streams, wherein a number second data streams is less than a number of first data streams;
• locking, by second circuitry, to the AMs in the second data streams;
• providing, by the second circuitry, data in the second streams to forward error correction (FEC) encoder circuitry;
• encoding, by the FEC encoder circuitry, data from the second circuitry according to an FEC code to generate FEC codewords;
• and
• generating, by third circuitry, the single output data stream based on the FEC codewords generated by the FEC encoding circuitry.