Transmission method, reception method, transmitter, and receiver
AssigneePanasonic Intellectual Property Corporation of America
InventorsYutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
Life of this patent
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Abstract
In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.
Claims2
A transmission method comprising:
- performing BCH (Bose-Chaudhuri-Hocquenghem) encoding on an information bit sequence to generate a first encoded bit sequence;
- inserting padding bits into the first encoded bit sequence to generate a padded bit sequence;
- performing LDPC (Low-Density Parity-Check) encoding on the padded bit sequence to generate a second encoded bit sequence;
- interleaving the second encoded bit sequence to generate an interleaved bit sequence;
- removing the padding bits from the interleaved bit sequence to generate a removed bit sequence;
- and
- transmitting the removed bit sequence, wherein
- the padded bit sequence includes first padding bits and the second padding bits, the first padding bits being inserted between a part of the first encoded bit sequence and another part of the first encoded bit sequence, the second padding bits being inserted after the first encoded bit sequence.
A transmission apparatus comprising:
- a processor that, in operation, performs:
- performing BCH (Bose-Chaudhuri-Hocquenghem) encoding on an information bit sequence to generate a first encoded bit sequence;
- inserting padding bits into the first encoded bit sequence to generate a padded bit sequence;
- performing LDPC (Low-Density Parity-Check) encoding on the padded bit sequence to generate a second encoded bit sequence;
- interleaving the second encoded bit sequence to generate an interleaved bit sequence;
- and
- removing the padding bits from the interleaved bit sequence to generate a removed bit sequence;
- and
- a transmitter that, in operation, transmits the removed bit sequence, wherein
- the padded bit sequence includes first padding bits and the second padding bits, the first padding bits being inserted between a part of the first encoded bit sequence and another part of the first encoded bit sequence, the second padding bits being inserted after the first encoded bit sequence.
Dependencies are inferred from the claim text.