US 12,750,158 B2Granted

Extended reality aggregator low latency robust error recovery

AssigneeQUALCOMM Incorporated

InventorsAbhijeet Dey, Wesley James Holland, Joby Abraham, Vijayamanohar Nagarajan

Life of this patent

Estimating the term…

Loading patent…

Abstract

Aspects of the disclosure are directed to error recovery. In accordance with one aspect, an apparatus includes a plurality of sensors configured to generate a plurality of sensor data; a plurality of sensor interfaces, wherein each one of the plurality of sensor interfaces is coupled to each one of the plurality of sensors; and an aggregator, coupled to the plurality of sensor interfaces, the aggregator configured a) to multiplex the plurality of sensor data into a single aggregator output stream, b) to detect a transmission error in the plurality of sensor data, and c) to recover the transmission error using an aggregator hardware without software involvement.

Claims30

Dependent claims

An apparatus for error recovery, the apparatus comprising:

a plurality of sensors configured to generate a plurality of sensor data;
a plurality of sensor interfaces, wherein each one of the plurality of sensor interfaces is coupled to each one of the plurality of sensors;
an aggregator, coupled to the plurality of sensor interfaces, the aggregator configured a) to multiplex the plurality of sensor data into a single aggregator output stream, b) to detect a transmission error due to a bit error or a bit erasure in the plurality of sensor data, c) to send an error flag message using a multiplexed data stream;
wherein the aggregator uses an aggregator hardware without software involvement;
and
a processing unit coupled to the aggregator, the processing unit configured to recover the transmission error using a processor hardware without software involvement and to substitute an errored pixel with a dummy pixel upon receipt of the error flag message from the multiplexed data stream, wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset.

3 more elements

A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement error recovery, the computer executable code comprising:

instructions for causing a computer to detect a packet data corruption event due to a bit error or a bit erasure in a series of frames of data transmission from a plurality of sensors;
instructions for causing the computer to determine if the packet data corruption event is an errored pixel or an errored line in the series of frames of data transmission from the plurality of sensors;
instructions for causing the computer to send an error flag message on a multiplexed data stream to provide packet data corruption event notification;
instructions for causing the computer to substitute an errored pixel with a dummy pixel upon receipt of the error flag message on the multiplexed data stream, wherein the dummy pixel enables an error recovery scheme for maintenance of a data packet dimension and wherein the maintenance avoids a hardware violation and avoids a reset;
and
instructions for causing the computer to send an error flag message to notify a plurality of processors of a presence and a location of the dummy pixel or the dummy line in the series of frames of data transmission from the plurality of sensors.

3 more elements

Dependencies are inferred from the claim text.