Phase-locked loop device, and operating method of the device

A method for operating a phase-locked loop device, the method comprising:

• receiving a reference clock signal and a first phase division signal divided from an output clock signal;
• generating a hold voltage based on a phase difference between the first phase division signal and the reference clock signal;
• generating a first conversion current based on the hold voltage;
• generating a status signal based on whether the phase difference is included in a predetermined interval;
• generating a second conversion current based on the status signal;
• providing a voltage control signal based on a conversion current including the first conversion current and the second conversion current;
• and
• providing the output clock signal based on the voltage control signal.

A phase-locked loop device, comprising:

• a first circuit comprising:
• a first flip-flop configured to output a first latch signal as a first selection signal based on a first adjustment clock signal, wherein a phase of the first adjustment clock signal is adjusted from a reference clock signal,
• a second flip-flop configured to output a second latch signal as a second selection signal based on a second adjustment clock signal, wherein a phase of the second adjustment clock signal is adjusted from the reference clock signal,
• a first AND gate configured to perform an AND operation on the first latch signal and the first selection signal to output a first status signal, a second AND gate configured to perform an AND operation on the second latch signal and the second selection signal to output a second status signal, and a NOR gate configured to perform a NOR operation on the first selection signal and the second selection signal to output a third selection signal;
• a second circuit comprising:
• a sampling phase detection circuit configured to provide a sampling voltage to a hold node based on the third selection signal,
• an up switch configured to provide a first supply voltage to the hold node based on the first selection signal, and
• a down switch configured to provide a second supply voltage different from the first supply voltage to the hold node based on the second selection signal;
• and
• a charge pump configured to output at least a portion of a conversion current based on the first status signal and the second status signal.