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US 12,750,060 B2Granted
Memory device and storage device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsTongsung Kim, Hyeseong Shin, Hyunwoo Ahn, Seonkyoo Lee, Hyunsung Lee, Daechul Jeong
Life of this patent
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Abstract
A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).
Claims20
A memory device, comprising:
- a memory chip configured to perform a phase calibration operation and a duty cycle correction operation, during a training section, said memory chip comprising:
- a first loop circuit, including:
- a phase detector configured to generate a first comparison signal by detecting a phase difference between a first signal and a second signal, which are received from external the memory chip;
- a first counter configured to generate a delay signal in response to the first comparison signal;
- and
- a delay cell configured to perform the phase calibration operation on the first signal, in response to the delay signal;
- and
- a second loop circuit, including:
- a phase generator configured to generate a second reverse signal in response to the second signal;
- the phase detector configured to generate a second comparison signal by comparing a duty cycle of a first reverse signal received from external the memory chip with a duty cycle of the second reverse signal;
- a second counter configured to generate a control signal in response to the second comparison signal;
- and
- a duty correction circuit (DCC) configured to perform the duty cycle correction operation on the second signal according to the control signal.
10 more elements
A storage device, comprising:
- a controller configured to provide a first signal, a second signal, and a first reverse signal;
- and
- a memory device configured to perform a phase calibration operation and a duty cycle correction operation, said memory device comprising:
- a phase detector configured to detect a phase difference between the first signal and the second signal;
- a first counter configured to generate a delay signal, based on the phase difference;
- a delay cell configured to receive the delay signal and perform a phase calibration operation on the first signal;
- a phase generator configured to generate a second reverse signal, based on the second signal;
- a second counter configured to, based on a difference generated by comparing a duty cycle of the first reverse signal with a duty cycle of the second reverse signal, generate a control signal;
- and
- a duty correction circuit (DCC) configured to receive the control signal and perform a duty cycle correction operation on the second signal.
7 more elements
A memory device, comprising:
- a plurality of memory chips;
- and
- an interface chip configured to perform communication between a controller and the plurality of memory chips;
- wherein the interface chip comprises a first loop circuit configured to perform a phase calibration operation during a training section of the controller, and a second loop circuit configured to perform a duty cycle correction operation during the training section of the controller;
- wherein the first loop circuit comprises:
- a phase detector configured to detect a phase difference between a first signal and a second signal, which are received from the controller, and generate a first comparison signal;
- a first counter configured to generate a delay signal, based on the first comparison signal;
- and
- a delay cell configured to perform the phase calibration operation on the first signal according to the delay signal;
- and
- wherein the second loop circuit comprises:
- a phase generator configured to generate a second reverse signal based on the second signal;
- the phase detector configured to compare a duty cycle of a first reverse signal received from the controller with a duty cycle of the second reverse signal and generate a second comparison signal;
- a second counter configured to generate a control signal, based on the second comparison signal;
- and
- a duty correction circuit (DCC) configured to perform the duty cycle correction operation on the second signal according to the control signal.
13 more elements
Dependencies are inferred from the claim text.