Clocking system for a system on chip using PLL
AssigneeMicrosoft Technology Licensing, LLC
InventorsCharles Walter Boecker, Eric Douglas Groen, Subramanian Krishnamoorthy, Shaishav Achyut Desai, Gurupada Mandal, Ravi Shivnaraine, Jaskarn S. Johal
Life of this patent
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Abstract
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.
Claims20
A device, comprising:
- a phase locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) and a phase detector;
- and
- a voltage supply and transconductance (Gm) cell that, in operation, drains a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm cell,
- wherein the Gm cell, in operation, generates an open_loop signal based on the Iout drained from the VCO, and the open_loop signal is input into the phase detector of the PLL to switch the operation of the PLL between an open loop state and a closed loop state.
A clocking system, comprising:
- a phase locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) and a phase detector;
- and
- a plurality of voltage supply and transconductance (Gm) cells, wherein:
- each of the plurality of Gm cells is configured to receive a threshold voltage Vthres and a sensed voltage Vsup_sense as inputs,
- each of the plurality of Gm cells is configured to drain a current Iout from the VCO based on a difference between the Vsup_sense and the Vthres, and
- each of the plurality of Gm cells is configured to generate an open_loop signal based on the Iout drained from the VCO.
A system on chip, comprising:
- a phase locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) and a phase detector;
- and
- a voltage supply and transconductance (Gm) cell configured to drain a current Iout from the VCO based on a difference between a sensed voltage (Vsup_sense) and a threshold voltage (Vthres) input into the Gm cell,
- wherein the Gm cell is configured to generate an open_loop signal based on the Iout drained from the VCO, and the open loop signal is input into the phase detector of the PLL to switch the operation of the PLL between an open loop state and a closed loop state.
Dependencies are inferred from the claim text.