System on chip self-organizing gates and related self organizing logic gates and methods
AssigneeMemComputing, Inc.
InventorFabio Lorenzo Traversa
Life of this patent
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Abstract
System on chip self-organizing gates are provided. In one aspect, a self-organizing logic circuit includes a plurality of self-organizing logic gates and at least one control circuit configured to selectively connect the self-organizing logic gates to embed a problem in the self-organizing logic gates. The self-organizing logic circuit can further include an output circuit configured to read a solution to the problem from the self-organizing logic gates.
Claims20
A self-organizing logic circuit, comprising:
- a plurality of self-organizing logic gates;
- at least one control circuit configured to selectively connect the self-organizing logic gates to embed a problem in the self-organizing logic gates, the at least one control circuit comprising:
- a plurality of address lines;
- a bit line selector;
- and
- a gate terminal selector, wherein the bit line selector and the gate terminal selector are configured to electrically connect the self-organizing logic gates via the address lines to embed the problem in the self-organizing logic gates;
- and
- an output circuit configured to read a solution to the problem from the self-organizing logic gates.
A self-organizing logic circuit, comprising:
- a plurality of self-organizing logic gates, wherein each of the self-organizing logic gates comprises:
- a plurality of physical terminals, and
- a plurality dynamic correction circuits, each of the dynamic correction circuits configured to drive a state of one of the physical terminals based on a state of one or more other ones of the physical terminals, and each of the dynamic correction circuits comprising a diode device and one or more elemental logic gates;
- at least one control circuit configured to selectively connect the self-organizing logic gates to embed a problem in the self-organizing logic gates;
- and
- an output circuit configured to read a solution to the problem from the self-organizing logic gates.
A self-organizing logic gate, comprising:
- a plurality of physical terminals;
- and
- a plurality dynamic correction circuits, each of the dynamic correction circuits configured to drive a state of one of the plurality of physical terminals based on states of the remaining one or more physical terminals of the plurality of physical terminals, each of the dynamic correction circuits comprising a diode device and one or more elemental logic gates,
- wherein the plurality of dynamic correction circuits are configured to implement a logical OR operation of the self-organizing logic gate such that at least one of the plurality of physical terminals has a logic 1 state.
A self-organizing logic gate, comprising:
- a plurality of physical terminals;
- a plurality dynamic correction circuits, each of the dynamic correction circuits configured to drive a state of one of the plurality of physical terminals based on states of the remaining one or more physical terminals of the plurality of physical terminals;
- and
- a global feedback circuit configured to provide additional electrical energy to the plurality of physical terminals when the self-organizing logic gate is in an invalid state,
- wherein the plurality of dynamic correction circuits are configured to implement a logical OR operation of the self-organizing logic gate such that at least one of the plurality of physical terminals has a logic 1 state.
Dependencies are inferred from the claim text.