Combined class D amplifier and buck regulator

A circuit for amplifying a digital signal, the digital signal having been derived from an input signal having a signal envelope, comprising:

• a transducer configured to output a signal based upon a voltage signal applied to the transducer, and having a first end and a second end and an inductance;
• a first transistor having a gate, a source and a drain, the source connected to a voltage supply;
• a second transistor having a gate, a source and a drain, the drain connected to the drain of the first transistor and the first end of the transducer;
• a third transistor having a gate, a source and a drain, the drain connected to the second end of the transducer;
• a fourth transistor having a gate, a source and a drain, the source connected to the voltage supply and the drain connected to the drain of the third transistor and the second end of the transducer;
• a fifth transistor having a gate, a source and a drain, the drain connected to the drain of the first transistor, the drain of the second transistor and the first end of the transducer, and the source connected to a ground;
• a sixth transistor having a gate, a source and a drain, the drain connected to the drain of the first transistor, the drain of the second transistor, the drain of the fifth transistor and the first end of the transducer,
• a seventh transistor having a gate, a source and a drain, the drain connected to the drain of the third transistor, the drain of the fourth transistor and the second end of the transducer,
• an eighth transistor having a gate, a source and a drain, the drain connected to the drain of the third transistor, the drain of the fourth transistor, the drain of the seventh transistor and the second end of the transducer, and the source connected to a ground;
• a capacitor having a first end and a second end, the first end connected to the source of the second transistor, the source of the third transistor, the source of the sixth transistor and the source of the seventh transistor, and the second end connected to the ground;
• and
• a control circuit connected to the gates of each of the eight transistors and configured to turn the transistors on and off to provide the transducer with a sequence of voltage pulses based upon an input signal, each voltage pulse being at one of a plurality of discrete values defined by the states of the transistors, the average value of the voltage pulses over time following the signal envelope and supplying the transducer with a voltage that causes the transducer to output an amplified signal;
• wherein the control circuit configured to turn the transistors on and off comprises a finite state machine configured to, based upon the digital signal and a charge on the capacitor and upon receipt of a sequence of control signals, turn the transistors on and off to provide the transducer with the sequence of voltage pulses, each voltage pulse corresponding to a value of the digital signal when each control signal is received and charge or discharge the capacitor.