Amplifier with source degeneration

An amplifier circuit, comprising:

• an input pair of transistors including a first transistor and a second transistor, the transistors in the input pair of transistors having respective source, drain, gate and bulk terminals;
• a resistor circuit connected to the sources of the transistors in the input pair of transistors, the resistor circuit including:
• a first MOS transistor having a first channel terminal connected to the source of the first transistor in the input pair of transistors, and a second channel terminal connected to the bulk terminal of the first transistor in the input pair of transistors;
• and
• a second MOS transistor having a first channel terminal connected to the source of the second transistor in the input pair of transistors, and a second channel terminal connected to the bulk terminal of the second transistor in the input pair of transistors;
• circuits to bias the first MOS transistor and the second MOS transistor in a triode region;
• and
• a current source connected to provide current through the resistor circuit to the input pair of transistors.

A method to receive an input signal, the method comprising:

• applying the input signal to an equalizer that includes:
• an input pair of transistors including a first transistor and a second transistor, the transistors in the input pair of transistors having respective source, drain, gate and bulk terminals, and
• a resistor circuit connected to the sources of the transistors in the input pair of transistors, the resistor circuit including:
• a first MOS transistor having a first channel terminal connected to the source of the first transistor in the input pair of transistors, and a second channel terminal connected to the bulk terminal of the first transistor in the input pair of transistors, and
• a second MOS transistor having a first channel terminal connected to the source of the second transistor in the input pair of transistors, and a second channel terminal connected to the bulk terminal of the second transistor in the input pair of transistors, and
• circuits to bias the first MOS transistor and the second MOS transistor in a triode region, and
• a current source connected to provide current through the resistor circuit to the transistors in the input pair of transistors, and
• wherein a bulk terminal of at least one of the first MOS transistor and the second MOS transistor in the resistor circuit is connected to the bulk terminal of at least one of the transistors in the input pair of transistors;
• and
• biasing at least one of the first MOS transistor and the second MOS transistor in the resistor circuit in a triode region.