High-density and high-voltage-tolerable pure core memory cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKu-Feng Lin, Perng-Fei Yuh, Meng-Sheng Chang
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Abstract
In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.
Claims20
A method for operating a memory device, comprising:
- receiving, through a first bit line coupled to a first memory cell, a first bit line signal;
- receiving, through a second bit line coupled to a second memory cell, a second bit line signal;
- receiving, through a word line coupled to a common transistor shared by the first memory cell and the second memory cell, a word line signal;
- receiving, through a first cascode gate line coupled to the first memory cell, a first cascode gate signal;
- and
- receiving, through a second cascode gate line coupled to the second memory cell, a second cascode gate signal.
A method for operating a memory device, comprising:
- receiving, through a first bit line coupled to a first memory cell including a first transistor and a first storage element, a first bit line signal;
- receiving, through a second bit line coupled to a second memory cell including a second transistor and a second storage element, a second bit line signal;
- and
- receiving, through a word line coupled to a common transistor shared by the first memory cell and the second memory cell, a word line signal;
- wherein the first memory cell is coupled between the first bit line and a center node, the second memory cell is coupled between the second bit line and the center node, and the common transistor is connected between the center node and a reference node.
A method for operating a memory device, comprising:
- receiving, through a first bit line coupled to a first memory cell including a first transistor and a first storage element, a first bit line signal;
- receiving, through a second bit line coupled to a second memory cell including a second transistor and a second storage element, a second bit line signal;
- and
- receiving, through a word line coupled to a common transistor shared by the first memory cell and the second memory cell, a word line signal;
- wherein the first memory cell is coupled between the first bit line and a first source/drain of the common transistor, the second memory cell is coupled between the second bit line and the first source/drain of the common transistor, and a second source/drain of the common transistor is connected to a ground node.
Dependencies are inferred from the claim text.