Operation method of memory, and memory, memory system, and electronic system

An operation method of a memory, comprising:

• acquiring a data output command, wherein the data output command carries a data output sequence corresponding to each of a plurality of memory planes in the memory;
• in response to the data output command, boosting voltages on all word lines corresponding to each of the plurality of memory planes to pass voltages in a voltage boosting rate corresponding to each of the plurality of memory planes to complete pre-charging of the plurality of memory planes,
• wherein either:
• the voltage boosting rate corresponding to the memory plane of which the data output sequence is a first sequence is greater than an average number, wherein the average number is a ratio of a total number of charge pump cells that have been configured in the memory to a number of the plurality of memory planes;
• or
• the voltage boosting rate corresponding to the memory plane of which the data output sequence is the first sequence is equal to the average number, and
• wherein a sum of the voltage boosting rates corresponding to the plurality of memory planes is less than a total average boosting rate configured by the memory, and
• wherein the voltage boosting rate is controlled by the charge pump cells;
• and
• for any one of the memory planes that has been pre-charged:
• reading data of the any one of the memory planes;
• and
• outputting the data of the any one of the memory planes according to the data output sequence corresponding to the any one of the memory planes,
• wherein when the data output sequence corresponding to the any one of the memory planes is the first sequence, read completion time corresponding to the any one of the memory planes is the same as output start time corresponding to the any one of the memory planes.

A memory, comprising:

• a memory array comprising a plurality of memory planes;
• a plurality of word lines coupled with memory cells in the plurality of memory planes;
• and
• a peripheral circuit coupled with the plurality of word lines, wherein the peripheral circuit is configured to perform an operation method of the memory, wherein the method comprises:
• acquiring a data output command, wherein the data output command carries a data output sequence corresponding to each of a plurality of memory planes in a memory;
• in response to the data output command, utilizing charge pump cells corresponding to each of the plurality of memory planes to boost voltages on all word lines corresponding to each of the plurality of memory planes to pass voltages to complete pre-charging of the plurality of memory planes,
• wherein either:
• a number of the charge pump cells corresponding to the memory plane of which the data output sequence is a first sequence is greater than an average number, wherein the average number is a ratio of a total number of charge pump cells that have been configured in the memory to a number of the plurality of memory planes;
• or
• the number of the charge pump cells corresponding to the memory plane of which the data output sequence is the first sequence is equal to the average number, and
• wherein a total number of the charge pump cells corresponding to the plurality of memory planes is less than the total number of charge pump cells that have been configured in the memory;
• and
• for any one of the memory planes that has been pre-charged:
• reading data of the any one of the memory planes;
• and
• outputting the data of the any one of the memory planes according to the data output sequence corresponding to the any one of the memory planes,
• wherein when the data output sequence corresponding to the any one of the memory planes is the first sequence, read completion time corresponding to the any one of the memory planes is the same as output start time corresponding to the any one of the memory planes.