Memory device, memory system including the same, and operating method of the memory device

A memory system comprising:

• a memory controller;
• and
• a memory device comprising:
• a voltage generator configured to generate voltages for a plurality of program loops for memory cells, wherein each of the plurality of program loops comprises a program operation and at least one verify operation, wherein the verify operation uses one of a plurality of verify voltages for verifying a plurality of program states;
• a plurality of memory cell planes each comprising a plurality of memory cells, the plurality of memory cell planes each configured to perform the plurality of program loops in response to the plurality of verify voltages and output a determination result corresponding to the at least one verify operation for each of the plurality of program loops;
• and
• control logic configured to control the plurality of memory cell planes based on the determination result,
• wherein the control logic is configured to based on the determination result regarding a first program loop of the plurality of program loops in which (i) a first memory cell plane of the plurality of memory cell planes is determined to be program-passed and (ii) a second memory cell plane of the plurality of memory cell planes is determined to be program-failed through a first verify voltage of the plurality of verify voltages for a first program state of the plurality of program states, control the memory cell planes such that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop of the plurality of program loops performed sequentially after the first program loop.

An operating method of a memory device, wherein the memory device comprises:

• a voltage generator configured to generate voltages for a plurality of program loops for a plurality of memory cells, wherein each of the plurality of program loops comprises a program operation and at least one verify operation, wherein the at least one verify operation uses one of a plurality of verify voltages for verifying a plurality of program states;
• a plurality of memory cell planes each comprising a plurality of memory cells, the plurality of memory cell planes each configured to perform the plurality of program loops in response to the plurality of verify voltages and output a determination result corresponding to the at least one verify operation for each of the plurality of program loops;
• and
• control logic configured to control the plurality of memory cell planes based on the determination result,
• wherein the operating method comprises:
• receiving a determination result for a first program loop of the plurality of program loops in which a first memory cell plane of the plurality of memory cell planes is determined to be program-passed and a second memory cell plane of the plurality of memory cell planes is determined to be program-failed through a first verify voltage of the plurality of verify voltages for a first program state of the plurality of program states;
• and
• controlling the plurality of memory cell planes so that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop of the plurality of program loops performed sequentially after the first program loop.