3D memory block having low-resistance source/drain buried layer stacked architecture

A memory block, comprising:

• a memory array, comprising:
• a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction;
• wherein each column of stacked strip structure extends along a column direction and comprises at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction;
• each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure comprises a low-resistance conductive structure;
• each column of semiconductor stacked strip structure at a non-edge position comprises a first semiconductor substructure, a second semiconductor substructure, and an insulating isolation structure arranged between the first semiconductor substructure and the second semiconductor substructure;
• each drain region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first drain region semiconductor sub-strip and a second drain region semiconductor sub-strip;
• each channel semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first channel semiconductor sub-strip and a second channel semiconductor sub-strip;
• each source region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first source region semiconductor sub-strip and a second source region semiconductor sub-strip;
• and
• each of the first drain region semiconductor sub-strip and the second drain region semiconductor sub-strip comprises a first drain region semiconductor layer structure, a second drain region semiconductor layer structure, and a third drain region semiconductor layer structure;
• the second drain region semiconductor layer structure is arranged between the first drain region semiconductor layer structure and the third drain region semiconductor layer structure;
• the first drain region semiconductor layer structure and the third drain region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second drain region semiconductor layer structure is of a silicon germanium semiconductor layer structure;
• and/or
• each of the first source region semiconductor sub-strip and the second source region semiconductor sub-strip comprises a first source region semiconductor layer structure, a second source region semiconductor layer structure, and a third source region semiconductor layer structure;
• the second source region semiconductor layer structure is arranged between the first source region semiconductor layer structure and the third source region semiconductor layer structure;
• the first source region semiconductor layer structure and the third source region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second source region semiconductor layer structure is of a silicon germanium semiconductor layer structure.