Memory devices including row decoder circuits having sub-word line driver circuit with nor logic circuit

A memory device, comprising:

• a core peripheral circuit structure comprising a first bonding metal pad;
• and
• a cell array structure at least partially overlapping the core peripheral circuit structure in a vertical direction, perpendicular to an upper surface of the core peripheral circuit structure, and comprising a second bonding metal pad in electrical contact with the first bonding metal pad,
• wherein the cell array structure comprises a memory cell region including a plurality of memory blocks comprising a plurality of word lines, wherein each of the plurality of word lines electrically contacts the first bonding metal pads and the second bonding metal pads, respectively,
• the core peripheral circuit structure comprises a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks, and
• the row decoder comprises:
• a main word line driver circuit configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals;
• and
• a sub-word line driver circuit configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are electrically connected, wherein the main word line driver circuit comprises:
• a first main word line driving signal generation circuit configured to generate the first main word line driving signals based on a first subset of signals of a most significant bit group from among the row address signals;
• a second main word line driving signal generation circuit configured to generate the second main word line driving signals based on a second subset of signals of a most significant bit group from among the row address signals, the second subset of signals of a most significant bit group are different from the first subset of signals of a most significant bit group;
• and
• a first sub-word line driving signal generation circuit and a second sub-word line driving signal generation circuit configured to generate first sub-word line driving signals and second sub-word line driving signals, respectively, based on remaining signals of a least significant bit group from among the row address signals.

A memory device, comprising:

• a core peripheral circuit structure comprising a first bonding metal pad;
• and
• a cell array structure at least partially overlapping the core peripheral circuit structure in a vertical direction, perpendicular to an upper surface of the core peripheral circuit structure, and comprising a second bonding metal pad in contact with the first bonding metal pad,
• wherein the cell array structure comprises a memory cell region including a plurality of memory blocks comprising a plurality of word lines, wherein each of the plurality of word lines electrically contacts the first bonding metal pads and the second bonding metal pads, respectively,
• the core peripheral circuit structure comprises a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks,
• the row decoder comprises a sub-word line driver circuit configured to activate one word line from among the plurality of word lines, and
• the sub-word line driver circuit is in a region that at least partially overlaps the first bonding metal pad in the vertical direction.