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US 12,749,518 B2Granted
Semiconductor devices with wrap-around arrays
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
Life of this patent
Estimating the term…
Abstract
A semiconductor device is presented. The semiconductor device includes a first memory mat associated with a first memory array segment and a first portion of a second memory array segment, a second memory mat disposed adjacent to the first memory mat, the second memory mat associated with a second portion of the second memory array segment and a first portion of a third memory array segment, and a third memory mat disposed adjacent to the second memory mat and on an opposite side to the first memory mat in the semiconductor device, the third memory mat associated with a second portion of the third memory array segment and a fourth memory array segment.
Claims20
A semiconductor device, comprising:
- a first memory mat associated with a first memory array segment and a first portion of a second memory array segment;
- a second memory mat disposed adjacent to the first memory mat, the second memory mat associated with a second portion of the second memory array segment and a first portion of a third memory array segment;
- and
- a third memory mat disposed adjacent to the second memory mat and on an opposite side to the first memory mat in the semiconductor device, the third memory mat associated with a second portion of the third memory array segment and a fourth memory array segment,
- wherein each one of the first, the second, the third, and the fourth memory array segments comprises a same number of memory sections, wherein the first memory array segment and the third memory array segment are paired so that word lines (WLs) of corresponding memory sections of the first memory array segment and the third memory array segment can be activated simultaneously, and wherein the second memory array segment and the fourth memory array segment are paired so that WLs of corresponding memory sections of the second memory array segment and the fourth memory array segment can be activated simultaneously.
2 more elements
A semiconductor device, comprising:
- a plurality of memory mats aligned along a word line (WL) extending direction, each one of the plurality of memory mats including a first number of memory sections aligned along a bit line (BL) extending direction, the BL extending direction being orthogonal to the WL extending direction;
- and
- a plurality of memory array segments, each one of the memory array segments is associated with a same second number of memory sections, the second number being smaller than the first number, wherein each of the plurality of memory array segments is associated with one or more of the plurality of memory mats,
- wherein each one of the plurality of memory mats is associated with at least a portion of a first memory array segment and a portion of a second memory array segment, and
- wherein WLs of memory sections of the portion of the first memory array segment and the portion of the second memory array segment are activated simultaneously.
2 more elements
A method of operating a semiconductor device, comprising:
- receiving a data read command and transmitting the data read command to a mat decoder of the semiconductor device, the data read command including address information;
- decoding, by the mat decoder, the received data read command to identify two or more memory array segments and memory sections within the identified memory array segments that data is stored in;
- transmitting the decoded memory array segment information and memory section information to each one of a plurality of row address decoders, the plurality of row address decoders being coupled to a plurality of memory mats included in the semiconductor device, respectively;
- enabling, by the mat decoder and based on the decoded memory array segment information and memory section information, one or more data sense amplifiers (DSA) of a plurality of DSAs that are connected to the plurality of memory mats, respectively;
- selecting, by the mat decoder and based on the decoded memory array segment information and memory section information, one or more multiplexers that are connected to corresponding DSA,
- activating word lines (WLs) associated with identified memory sections of the memory array segments;
- outputting data signals from identified memory sections to one or more data buses, the output data signals transmitting through enabled DSAs and one or more enabled multiplexers.
4 more elements
Dependencies are inferred from the claim text.