US 12,749,517 B2 · Flexible SRAM pre-charge systems and methods for minimizing leakage and reducing power consumption

Abstract

Embodiments of the present disclosure include techniques for pre-charging an SRAM. A pre-charge signal may be used to apply a pre-charge voltage to bit lines in an SRAM memory bank. Features and advantages of the present disclosure include receiving a pre-charge signal in an SRAM and storing the pre-charge signal. The pre-charge signal may be received and stored on a cycle where the SRAM is performing a memory access. The stored pre-charge signal may be applied on a later cycle. In some embodiments, an SRAM is partitioned into multiple sub-banks, and multiple pre-charge signals are received and stored for different sub-banks. Stored pre-charge signals may be applied to the different sub-banks independently, for example.

Claims19

Dependent claims

A static random access memory (SRAM) circuit comprising:

an SRAM memory bank configured to store bits of data, the SRAM memory bank comprising a plurality of bit lines;
and
an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to pre-charge the plurality of bit lines to access the stored bits of data,
wherein the SRAM access control circuit receives, at a pre-charge request input, and stores a pre-charge signal for a subsequent cycle while the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle, and
wherein the SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/154,436Filed 13 Jan 2023

Published

US 2024/0242748 A118 Jul 2024

Granted

29 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 7/24
Arrangements for writing information into, or reading information out from, a digital store: memory cell safety or protection circuits, e.g.…
G11C 5/148
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: details…
G11C 7/1042
Read-write modes for single port memories, i.e. having either a random port or a serial port: using interleaving techniques, i.e. read-write of…
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…

Flexible SRAM pre-charge systems and methods for minimizing leakage and reducing power consumption

Life of this patent

Flexible SRAM pre-charge systems and methods for minimizing leakage and reducing power consumption

Life of this patent

Abstract

Claims19