Display apparatus
AssigneeLG Display Co., Ltd.
InventorsSeung Hwan Shin, Hwa Young Kim
Life of this patent
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Abstract
A display apparatus includes a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged, and the plurality of gate lines is divided into at least two regions and separately driven, at least two gate drivers configured to supply scan signals at different frequencies to the plurality of gate lines of the divided regions, a data driver configured to supply data signals to the plurality of data lines, and a controller configured to control the at least two gate drivers such that the at least two gate drivers output scan signals at different frequencies.
Claims20
A display apparatus comprising:
- a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged, wherein the plurality of gate lines is divided into at least two regions configured to be separately driven;
- at least two gate drivers configured to supply scan signals at different frequencies to the plurality of gate lines of the at least two regions;
- a data driver configured to supply data signals to the plurality of data lines;
- and
- a controller configured to control the at least two gate drivers such that the at least two gate drivers output scan signals at different frequencies,
- wherein the at least two gate drivers include a first gate driver and a second gate driver, the first gate driver is configured to drive gate lines of a relevant region at a first frequency, and the second gate driver is configured to drive gate lines of a relevant region at a second frequency lower than the first frequency, and
- wherein the controller is configured to control the second gate driver to skip an arbitrary frame.
A display apparatus comprising:
- a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged, wherein the plurality of gate lines is divided into at least two regions configured to be separately driven;
- at least two gate drivers configured to supply scan signals at different frequencies to the plurality of gate lines of the at least two regions;
- a data driver configured to supply data signals to the plurality of data lines;
- and
- a controller configured to control the at least two gate drivers such that the at least two gate drivers output scan signals at different frequencies,
- wherein the at least two gate drivers each include a plurality of cascadedly connected stages,
- wherein each stage comprises:
- a first output transistor configured to output one of a plurality of clock signals to an output terminal in response to a signal of a Q node;
- a second output transistor configured to output a gate high voltage to the output terminal in response to a signal of a QB node;
- a Q node controller configured to control a voltage of the Q node using a start signal, a reset signal, and a gate low voltage;
- and
- a QB node controller configured to control a voltage of the QB node using the start signal, the reset signal, another one of the plurality of clock signals, and the gate low voltage.
A gate driver circuitry comprising a plurality of cascadedly connected stages,
- wherein each stage comprises:
- a first output transistor configured to output one of a plurality of clock signals to an output terminal in response to a signal of a Q node;
- a second output transistor configured to output a gate high voltage to the output terminal in response to a signal of a QB node;
- a Q node controller configured to control a voltage of the Q node using a start signal, a reset signal, and a gate low voltage;
- and
- a QB node controller configured to control a voltage of the QB node using the start signal, the reset signal, another one of the plurality of clock signals, and the gate low voltage.
Dependencies are inferred from the claim text.