Systems and methods for implementing neuromorphic computing

A system for implementing neuromorphic computing using analog Kolmogorov-Arnold Network (KAN) in standard complementary metal-oxide-semiconductor (CMOS) technology, the system comprising:

• an analog KAN comprising a plurality of interconnected KAN nodes, each KAN node being configured to approximate a nonlinear function, respectively;
• and
• a circuit architecture implemented using the standard CMOS technology, the circuit architecture being configured to support operation of the analog KAN,
• the analog KAN further comprising:
• a mathematical model based on Kolmogorov-Arnold representation theorem configured to realize KANs for executing a neuromorphic computing operation;
• and
• a nonlinear transistor network configured to realize the mathematical model, the nonlinear transistor network comprising nonlinear voltage-controlled current sources and passive impedance elements,
• the analog KAN further comprising a continuous-state KAN configured to process internal signals as continuous analog values rather than discrete digital states, thereby eliminating linearization requirements associated with multilayer perceptron architectures,
• the analog KAN being configured to perform both training and inference operations utilizing analog-domain signals and analog hardware components, the analog KAN functioning as an analog circuit accelerator for neural network computation,
• the analog-domain signals comprising continuous-time and continuous-amplitude electrical signals configured to represent and process information without digitization,
• the analog hardware components comprising physical circuit elements configured to generate, process, or manipulate the analog-domain signals without requiring analog-to-digital conversion or digital-to-analog conversion,
• the analog KAN being configured for efficient implementation in the standard CMOS technology through use of a multi-input, multi-field-effect transistor (FET) small-signal amplifier to compute analog dot products,
• the multi-input, multi-FET small-signal amplifier being configured to implement mathematical operations of the KAN, and the multi-input, multi-FET small-signal amplifier comprising a multi-FET structure with multiple inputs for simultaneous processing of distinct signals, operating under small-signal conditions, performing nonlinear transformations, and enabling efficient analog computation,
• each KAN node being designed for minimal on-chip complexity, thereby reducing chip area and power consumption through low transistor counts relative to conventional neural circuits, and each KAN node comprising:
• (i) a first transistor configured to regulate current flow based on an external control voltage applied to a gate terminal of the first transistor;
• and
• (ii) two additional transistors configured to modulate or reprogram magnitude of control current by managing current paths within the KAN node, thereby enabling dynamic tuning of the control current, and
• the nonlinear functions being implemented using analog circuit elements configured to exploit nonlinearities arising from intrinsic semiconductor physics of CMOS transistors and metal-oxide-semiconductor (MOS) capacitors, the nonlinear functions being utilized without requiring user configuration.