Analog hardware realization of neural networks

A system for hardware realization of neural networks, comprising:

• one or more processors;
• memory;
• wherein the memory stores one or more programs configured for execution by the one or more processors, and the one or more programs comprising instructions for:
• obtaining a neural network topology and weights of a trained neural network;
• transforming the neural network topology to an equivalent analog network of analog components corresponding to the neural network, including:
• selecting a plurality of individual electronic analog components, wherein the plurality of individual analog components include components corresponding to analog neurons and components corresponding to connections between pairs of analog neurons;
• computing a first weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between a respective pair of analog neurons;
• generating a first schematic model for implementing the equivalent analog network as electronic circuitry based on the weight matrix, wherein:
• generating the first schematic model includes generating a first resistance matrix from the weight matrix, each element of the first resistance matrix (i) representing a respective fixed resistance value, (ii) corresponding to a respective weight of the weight matrix, and (iii) defining a respective single predetermined signal pathway between a respective pair of analog neurons:
• the first schematic model includes a first portion corresponding to topology of analog neurons and a second portion corresponding to connections between the analog neurons;
• and
• generating the first schematic model includes:
• selecting component values for each analog neuron;
• and
• assigning fixed values to the connections based on the weight matrix;
• obtaining new weights for an updated neural network that corresponds to the trained neural network after it has been re-trained;
• computing a new weight matrix for an equivalent analog network corresponding to the updated neural network based on the new weights;
• generating a new resistance matrix for the new weight matrix;
• and
• generating a new schematic model for implementing the equivalent analog network of analog components corresponding to the updated neural network based on the new resistance matrix, so that:
• a first set of one or more lithographic masks generated for fabricating the neural network includes one or more first lithographic masks corresponding to the first portion of the first schematic model and a second lithographic mask corresponding to the second portion of the first schematic model;
• and
• a second set of one or more lithographic masks generated for fabricating the updated neural network includes the one or more first lithographic masks corresponding to the first portion of the first schematic model and a third lithographic mask corresponding to the second portion of the new schematic model, wherein:
• the topology of analog neurons for the updated neural network is the same as the topology of analog neurons for the neural network prior to updating:
• the new schematic model includes a third portion corresponding to topology of analog neurons and a fourth portion corresponding to connections between the analog neurons for the updated neural network;
• the third portion of the new schematic model is the same as the first portion of the first schematic model;
• and
• the fourth portion of the new schematic model is different from the second portion of the first schematic model.

A non-transitory computer readable storage medium storing one or more programs configured for execution by a computer system having one or more processors, the one or more programs comprising instructions for:

• obtaining a neural network topology and weights of a trained neural network;
• transforming the neural network topology to an equivalent analog network of analog components corresponding to the neural network, including:
• selecting a plurality of individual electronic analog components, wherein the plurality of individual analog components include components corresponding to analog neurons and components corresponding to connections between pairs of analog neurons;
• computing a first weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between a respective pair of analog neurons;
• generating a first schematic model for implementing the equivalent analog network as electronic circuitry based on the weight matrix, wherein:
• generating the first schematic model includes generating a first resistance matrix from the weight matrix, each element of the first resistance matrix (i) representing a respective fixed resistance value, (ii) corresponding to a respective weight of the weight matrix, and (iii) defining a respective single predetermined signal pathway between a respective pair of analog neurons;
• the first schematic model includes a first portion corresponding to topology of analog neurons and a second portion corresponding to connections between the analog neurons;
• and
• generating the first schematic model includes:
• selecting component values for each analog neuron;
• and
• assigning fixed values to the connections based on the weight matrix;
• obtaining new weights for an updated neural network that corresponds to the trained neural network after it has been re-trained;
• computing a new weight matrix for an equivalent analog network corresponding to the updated neural network based on the new weights:
• generating a new resistance matrix for the new weight matrix;
• and
• generating a new schematic model for implementing the equivalent analog network of analog components corresponding to the updated neural network based on the new resistance matrix, so that:
• a first set of one or more lithographic masks generated for fabricating the neural network includes one or more first lithographic masks corresponding to the first portion of the first schematic model and a second lithographic mask corresponding to the second portion of the first schematic model;
• and
• a second set of one or more lithographic masks generated for fabricating the updated neural network includes the one or more first lithographic masks corresponding to the first portion of the first schematic model and a third lithographic mask corresponding to the second portion of the new schematic model, wherein:
• the topology of analog neurons for the updated neural network is the same as the topology of analog neurons for the neural network prior to updating;
• the new schematic model includes a third portion corresponding to topology of analog neurons and a fourth portion corresponding to connections between the analog neurons for the updated neural network;
• the third portion of the new schematic model is the same as the first portion of the first schematic model;
• and
• the fourth portion of the new schematic model is different from the second portion of the first schematic model.