Physical unclonable function device and method

A method of operating a system, the method comprising:

• reading, with a processing circuit, effective threshold voltages of depletion-type state transistors of a plurality of memory cells of a physical unclonable function device, the plurality of memory cells being arranged in a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the first assembly of non-volatile memory cells being organized into two first matrix sub-assemblies disposed symmetrically with respect to a reading circuit, all rows of the two first matrix sub-assemblies being parallel, and the reading comprises differentially reading, by the reading circuit in the processing circuit, the effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies;
• accessing reliability information corresponding with the depletion-type state transistors of the non-volatile memory cells of the first assembly, wherein the reliability information is representative of a reliability or unreliability of contents of the non-volatile memory cells of the first assembly;
• generating, with the processing circuit, output data based on the effective threshold voltages and the reliability information, the output data being stored in a second assembly of non-volatile memory cells each having a second selection transistor embedded in the semiconductor substrate and a second depletion-type state transistor having a control gate and a floating gate, the non-volatile memory cells of the second assembly being configured to contain the reliability information;
• and
• delivering the output data to an output interface of the physical unclonable function device.

A method comprising:

• manufacturing an integrated circuit comprising a physical unclonable function device, said manufacturing of the physical unclonable function device including:
• providing a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the depletion-type state transistors having respective effective threshold voltages belonging to a common random distribution;
• and
• providing a processing circuit configured to deliver, to an output interface of the physical unclonable function device, a group of output data, wherein the group of output data is based on a reading of the respective effective threshold voltages of the depletion-type state transistors of the non-volatile memory cells of the first assembly, and is based on a corresponding group of reliability data corresponding with the depletion-type state transistors of the non-volatile memory cells of the first assembly, the processing circuit including
• a reading circuit configured to carry out the readings, the first assembly of non- volatile memory cells being organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel, the reading circuit being configured to carry out differential readings of pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies, and
• a second assembly of non-volatile memory cells each having a second selection transistor embedded in the semiconductor substrate and a second depletion-type state transistor having a control gate and a floating gate, the non-volatile memory cells of the second assembly configured to contain the reliability data, wherein the reliability data is representative of a reliability or unreliability of contents of the non-volatile memory cells of the first assembly.