Scalable detection of hardware Trojans using ATPG-based activation of rare events

A system for test pattern generation to detect a hardware Trojan comprising:

• a processor of a computing device;
• and
• a tangible, non-transitory memory configured to communicate with the processor, the tangible, non-transitory memory having instructions stored thereon that, in response to execution by the processor, cause the computing device to at least:
• simulate an integrated circuit design;
• during the simulation, identify rare nodes within the integrated circuit design that are activated less than a predefined rareness threshold, wherein the rare nodes include both signals and branches of the integrated circuit design;
• map each rare node to a stuck-at fault model;
• obtain a first set of N test vectors for each stuck-at fault model using Automated Test Pattern Generation, wherein each of the N test vectors activates a same rare node of the integrated circuit design, wherein the first set of N test vectors are obtained by:
• for each stuck-at fault model, determining a pilot test vector to activate the stuck-at fault model;
• and
• generating N−1 test vectors for each pilot test vector based on a constraint, wherein N−1 constraints are used to generate the N−1 test vectors, wherein each N−1 test vector activates a same stuck-at fault, thereby increasing a likelihood of activating the Hardware trojan;
• identify maximal cliques of rare nodes in the integrated circuit design that can be activated at a same time;
• and
• generate a second set of test vectors to activate each of the identified maximal cliques using Automated Test pattern Generation.

A non-transitory computer-readable medium having instructions stored therein, wherein the instructions, when executed by a processor, cause the processor to:

• simulate an integrated circuit design;
• during the simulation, identify rare nodes within the integrated circuit design that are activated less than a predefined rareness threshold, wherein the rare nodes include both signals and branches of the integrated circuit design;
• map each rare node to a stuck-at fault model;
• obtain a first set of N test vectors for each stuck-at fault model using Automated Test Pattern Generation, wherein each of the N test vectors activates a same rare node of the integrated circuit design, wherein the first set of N test vectors are obtained by:
• for each stuck-at fault model, determining a pilot test vector to activate the stuck-at fault model;
• and
• generating N−1 test vectors for each pilot test vector based on a constraint, wherein N−1 constraints are used to generate the N−1 test vectors, wherein each N−1 test vector activates a same stuck-at fault, thereby increasing a likelihood of activating a Hardware trojan;
• identify maximal cliques of rare nodes in the integrated circuit design that can be activated at a same time;
• and
• generate a second set of test vectors to activate each of the identified maximal cliques using Automated Test pattern Generation.