Data burst suspend mode using multi-level signaling
AssigneeMicron Technology, Inc.
InventorsEric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
Life of this patent
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Abstract
A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.
Claims14
A memory device comprising:
- a memory array;
- and
- processing logic, operatively coupled with the memory array, to perform operations comprising:
- initiating a data transfer across an interface bus by toggling a logical level of a control pin from a third level that inactivates the data transfer to a first level that activates the data transfer;
- causing the data transfer to be suspended by toggling the logical level of the control pin from the first level to a second level that suspends the data transfer;
- and
- causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level;
- wherein the first level has a magnitude greater than the second level and less than the third level.
A method comprising:
- initiating, by a processing device, a data transfer across an interface bus by toggling a logical level of a control pin from a third level that inactivates the data transfer to a first level that activates the data transfer;
- causing, by a processing device, a data transfer to be suspended by toggling the logical level of the control pin from the first level to a second level that suspends the data transfer;
- and
- causing, by the processing device, the data transfer to resume by toggling the logical level of the control pin from the second level to the first level;
- wherein the first level has a magnitude greater than the second level and less than the third level.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- initiating a data transfer across an interface bus by toggling a logical level of a control pin from a third level that inactivates the data transfer to a first level that activates the data transfer;
- causing the data transfer to be suspended by toggling the logical level of the control pin from the first level to a second level that suspends the data transfer;
- and
- causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level;
- wherein the first level has a magnitude greater than the second level and less than the third level.
Dependencies are inferred from the claim text.