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US 12,748,707 B1Granted
Row hammer effect mitigation through least row used buffering of writeback data
OwnerJames C. Maxtedinventor
Life of this patent
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Abstract
Buffering row data from multiple row read operations and delaying writeback of buffered row data to a cell array by writing back data from a least recently used register only when adding new row data would exceed the capacity of the row data buffer structure.
Claims19
A memory device comprising:
- a cell array comprising a plurality of rows for storing data;
- sense amplifiers configured to read data from a selected row of the cell array;
- a row data buffer structure operatively coupled to the sense amplifiers and the cell array, the row data buffer structure comprising:
- a plurality of registers, each register configured to store a row address and corresponding row data read from the cell array;
- content addressable memory (CAM) configured to compare a current row address with row addresses stored in the plurality of registers to determine if the corresponding row data is buffered;
- and
- least-recently-used (LRU) logic configured to track usage of the registers and manage storage of new row addresses and row data;
- wherein the row data buffer structure is configured to buffer row data from multiple row read operations and to delay writeback of buffered row data to the cell array by writing back data from a least recently used register only when adding new row data would exceed capacity of the row data buffer structure, thereby mitigating row hammer effects through temporal spacing of row activations.
5 more elements
A method for mitigating row hammer effects in a memory device having a cell array comprising a plurality of rows for storing data and sense amplifiers configured to read data from a selected row of the cell array, the method comprising:
- providing a row data buffer structure operatively coupled to the sense amplifiers and the cell array, the row data buffer structure comprising a plurality of registers, each register configured to store a row address and corresponding row data read from the cell array, content addressable memory (CAM) configured to compare a current row address with row addresses stored in the plurality of registers to determine if the corresponding row data is buffered, and least-recently-used (LRU) logic configured to track usage of the registers and manage storage of new row addresses and row data;
- buffering, using the row data buffer structure, row data from multiple row read operations;
- and
- delaying writeback of buffered row data to the cell array by writing back data from a least recently used register only when adding new row data would exceed capacity of the row data buffer structure, thereby mitigating row hammer effects through temporal spacing of row activations.
1 more element
Dependencies are inferred from the claim text.