Storage controller, storage device including the same, and operating method

A storage controller, comprising:

• a plurality of first data pins;
• processing circuitry configured to generate a first data pattern;
• and
• a logic circuit configured to,
• send a command including the generated first data pattern to a memory device through a command/address line, wherein the memory device is configured to generate a second data pattern based on the first data pattern included in the command;
• receive, in response to the memory device sending the second data pattern through a plurality of data lines, a third data pattern, the second data pattern generated based on the command;
• determine the second data pattern based on the command, independently from the memory device generating the second data pattern;
• and
• determine, based on the second data pattern and the third data pattern, a connection structure between the plurality of first data pins and a plurality of second data pins of the memory device, the plurality of first data pins being connected to the plurality of second data pins through the plurality of data lines.

A storage device, comprising:

• a storage controller including a plurality of first data pins, the storage controller configured to send a command through a command/address (CA) line, the command including a first data pattern;
• and
• a memory device including a plurality of second data pins connected to the plurality of first data pins through a plurality of data lines,
• wherein the memory device is configured to:
• receive, from the storage controller, the command including the first data pattern, and
• generate a second data pattern based on the first data pattern included in the command, and
• send the second data pattern to the storage controller through the plurality of data lines, and
• wherein the storage controller is configured to:
• receive a third data pattern in response to the memory device sending the second data pattern,
• determine the second data pattern based on the command, independently from the memory device generating the second data pattern, and
• determine a connection structure between the plurality of first data pins and the plurality of second data pins by comparing the second data pattern determined at the storage controller and the third data pattern received at the storage controller.