Tracking latch upset events using a trim register
AssigneeMicron Technology, Inc.
InventorsJohn M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.
Claims16
A method, comprising:
- reading static trim data from a static trim register in a non-volatile memory device;
- reading dynamic trim data from a dynamic trim register in the non-volatile memory device;
- generating parity data for the static trim data and the dynamic trim data;
- storing the parity data in the static trim register;
- and
- subsequent to the generation and storage of the parity data:
- re-reading the static trim data from the static trim register and the dynamic trim data from the dynamic trim register;
- generating additional parity data;
- comparing the parity data to the additional parity data;
- and
- in response to the parity data matching the additional parity data, determining that the static trim data and the dynamic trim data are valid.
An apparatus, comprising:
- a first memory device comprising trim registers configured to store trim data;
- a second memory device coupled to the first memory device;
- and
- a controller coupled to the first memory device and the second memory device, the controller configured to:
- read a first set of trim data from the first memory device;
- read a second set of trim data from the second memory device;
- compare the first set of trim data to the second set of trim data;
- and
- in response to the first set of trim data being different than the second set of trim data, write the second set of trim data in the second memory device over the first set of trim data in the first memory device.
An apparatus, comprising:
- a memory device comprising:
- a static trim register configured to store static trim data;
- and
- a dynamic trim register configured to store dynamic trim data;
- and
- a controller coupled to the memory device and configured to:
- read the static trim data from the static trim register;
- read the dynamic trim data from the dynamic trim register;
- generate parity data using the static trim data and the dynamic trim data;
- store the parity data in the static trim register;
- and
- subsequent to the generation and storage of the parity data:
- re-read the static trim data from the static trim register and the dynamic trim data from the dynamic trim register;
- generate additional parity data;
- and
- compare the parity data to the additional parity data.
Dependencies are inferred from the claim text.