System and method for opportunistic thread-switching for faster task-switching for handling interrupts and subroutines

A computing device, the computing device comprises:

• a single processor that is configured with at least one of processor-executable instructions or processor-executable microcode that configure the single processor to perform a method that includes at least:
• managing a plurality of threads that includes at least a first thread and a second thread, the plurality of threads managed using a thread register containing thread identifiers and indicating a canonical sequence of only active threads;
• causing the first thread to receive a priority task;
• responsive to the priority task, determining an availability status of the second thread using an availability status bit of an availability status register (ASR) associated with the second thread by thread identifier, the availability status being at least one of said active or idle;
• responsive to a determination that the second thread activity status is idle, copying a plurality of registers determined by register save bits of the first thread ASR, the plurality of registers associated with the first thread for use by the second thread, activating the second thread, and changing an availability status bit of the second thread ASR from idle to active;
• performing the priority task at least in part with the second thread;
• and
• responsive to completion of the priority task, deactivating the second thread and changing the availability status bit of the second thread from active to idle.

A method implemented with a computing device, the method comprising:

• with at least a single processor core of a fine grained, multi-threaded processor, managing a plurality of threads that includes at least a first thread and a second thread, the at least first thread and the second thread associated with thread identifiers in a thread register issuing a canonical sequence of thread identifiers, each thread identifier associated with an availability status register (ASR) having an availability status bit set to active;
• causing the first thread to receive a priority task;
• responsive to the priority task, determining an availability status of the second thread using the associated second thread ASR, the availability status being at least one of active or idle;
• responsive to a determination that the second thread activity status is idle, copying state associated with the first thread for use by the second thread, activating the second thread by including its thread identifier in the thread register, and changing the availability status bit of the second thread from idle to active, the state associated with the first thread comprising at least a plurality of registers, the plurality of registers determined by register save bits of the associated ASR;
• performing the priority task at least in part with the second thread;
• and
• responsive to completion of the priority task, deactivating the second thread and changing the availability status bit of the second thread from active to idle.