Interrupt controller, apparatus, interrupt control method and computer-readable medium

An apparatus comprising:

• the interrupt controller according to any preceding claim;
• the cache coherent interconnect;
• and
• at least one physical processor, a given physical processor comprising:
• processing circuitry to perform data processing in response to instructions;
• at least one processor cache;
• and
• processor memory access circuitry to issue memory access requests for accessing the shared memory system via the cache coherent interconnect.

An interrupt control method comprising:

• detecting interrupts raised by one or more interrupt sources;
• and
• in response to a given interrupt of a given interrupt identifier being detected, controlling signalling of the given interrupt to a target interrupt handling context, by controlling issuing of one or more memory write requests via a cache coherency interconnect in accordance with a coherency protocol, to maintain a set of memory-based interrupt tracking structures corresponding to the target interrupt handling context, the set of memory-based interrupt tracking structures including:
• a selected interrupt queue structure selected from among a plurality of interrupt queue structures based on the given interrupt identifier, to queue the given interrupt for processing by the target interrupt handling context;
• and
• a queue status summary structure to indicate which of the plurality of interrupt queue structures hold pending interrupts awaiting processing by the target interrupt handling context.