Reducing energy comsumption of self-managed DRAM modules
AssigneeScaleflux, Inc.
InventorsKelly Fitzpatrick, Yang Liu, Tong Zhang
Life of this patent
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Abstract
A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DRAM chips and a management engine configured to read and write data blocks to the DRAM chips, wherein a write operation is implemented according to a process that includes: allocating a sequential region of memory space in the DRAM chips; collecting sequential data in a write buffer; compressing a data chunk of sequential data from the write buffer to form a compressed data chunk; and writing the compressed data chunk to the sequential region.
Claims6
A method of implementing a self-managed dynamic random-access memory (DRAM) module, comprising:
- providing a plurality of DRAM chips;
- providing a controller chip configured to store either uncompressed data using channel/bank interleaving among a plurality of channels or compressed data sequentially along a single channel as sequential data;
- allocating a sequential region of memory space in the DRAM chips to store sequential data;
- storing data received during a write operation into a write buffer, and then:
- compressing and migrating the data to the sequential region of data if an older version of the data is currently stored in compressed form in the sequential region;
- or
- migrating the data to DRAM using channel/bank interleaving if an older version of the data is not currently stored in compressed form;
- recurringly evaluating, in the background, uncompressed data chunks stored using channel/bank interleaving to determine whether an uncompressed data chunk has been sequentially accessed over a time window during prior read operations;
- in response to the uncompressed data chunk being sequentially accessed over the time window, compressing the uncompressed data chunk to form a compressed data chunk;
- and
- writing the compressed data chunk to the sequential region.
A method of implementing a self-managed dynamic random-access memory (DRAM) module, comprising:
- providing a plurality of DRAM chips;
- providing a controller chip configured to store either uncompressed data using channel/bank interleaving among a plurality of channels or compressed data sequentially along a single channel as sequential data;
- allocating a sequential region of memory space in the DRAM chips to store sequential data;
- storing data received during a write operation into a write buffer, and then:
- compressing and migrating the data to the sequential region of data if an older version of the data is currently stored in compressed form in the sequential region;
- or
- migrating the data to DRAM using channel/bank interleaving if an older version of the data is not currently stored in compressed form;
- recurringly evaluating, in the background, compressed data chunks stored sequentially to determine whether a compressed data chunk has been sequentially accessed over a time window during previous read operations;
- in response to the compressed data chunk not being sequentially accessed over the time window, uncompressing the compressed data chunk to form an uncompressed data chunk;
- and
- writing the uncompressed data chunk using channel/bank interleaving among the plurality of channels.
Dependencies are inferred from the claim text.