Method and circuit for reducing processing latency

A host processor configured to execute a driver to arrange a set of descriptors in storage for access by a processor when executing a processing operation;

• the driver being configured to:
• provide a set of descriptors of a processing operation;
• each descriptor comprising address and attribute information for a referenced entity in storage;
• provide a hierarchical access structure comprising a plurality of tiers in storage, wherein a number of memory accesses associated with accessing a first tier is less than a number of memory accesses associated with accessing a second tier,
• for each descriptor, determine a latency attribute of the entity referenced by the descriptor;
• the latency attribute being indicative of a relative impact of accesses of the referenced entity on the overall processing latency of the processing operation;
• and
• for each descriptor, arrange the descriptor in the hierarchical access structure based on the latency attribute.