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US 12,748,476 B2Granted
Power management in multi-die SoCs through hardware power control
AssigneeApple Inc.
InventorsDoron Rajwan, Karl D. Wulcan, Tal Kuzi, Inder M. Sodhi, Achmed R. Zahir, Ilya Granovsky, Nir Leshem, Lior Zimet
Life of this patent
Estimating the term…
Abstract
Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.
Claims20
An integrated circuit, comprising:
- a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budgeted amount assigned to the given component;
- a trigger logic circuit configured to generate a power reduction signal based on receiving trigger signals input to the integrated circuit, wherein the power reduction signal is synchronous with a clock cycle of the integrated circuit, and wherein the power reduction signal applies power control across the plurality of components;
- a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals, wherein the rate control circuit reduces the clock rate asynchronously from the clock cycle;
- and
- a power management circuit configured to control the budgeted amount assigned to the given component based on assessment of the power control applied by the power reduction signal against a threshold.
2 more elements
A system comprising:
- an integrated circuit;
- and
- a power management unit coupled to the integrated circuit, wherein the power management unit is configured to supply power to the integrated circuit and to generate trigger signals;
- wherein the integrated circuit comprises:
- a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budgeted amount assigned to the given component;
- a trigger logic circuit configured to generate a power reduction signal based on receiving the trigger signals from the power management unit, wherein the power reduction signal applies power control across the plurality of components, and wherein the trigger logic circuit is configured to provide the power reduction signal to at least one additional integrated circuit;
- a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals;
- and
- a power management circuit configured to control the budgeted amount assigned to at least one of the plurality of components based on assessment of the power control applied by the power reduction signal against a threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the budgeted amount assigned.
6 more elements
A system comprising:
- an integrated circuit;
- and
- a power management unit coupled to the integrated circuit, wherein the power management unit is configured to supply power to the integrated circuit and to generate a trigger input;
- wherein the integrated circuit comprises:
- a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budgeted amount assigned to the given component, and wherein the plurality of components includes at least one memory controller circuit configured to control memory;
- a trigger logic circuit configured to generate a power reduction signal based on receiving the trigger input from the power management unit, and wherein the power reduction signal applies power control across the plurality of components;
- a plurality of rate limiter circuits at a plurality of locations in a pipeline within the at least one memory controller circuit, and wherein one or more of the plurality of rate limiter circuits is configured to limit a rate at which memory transactions flow through the plurality of locations;
- and
- a power management circuit configured to control the budgeted amount assigned to at least one of the plurality of components based on assessment of the power control applied by the power reduction signal against a threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the budgeted amount assigned.
6 more elements
Dependencies are inferred from the claim text.