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US 12,748,454 B2Granted
Reliable and fault-tolerant clock generation and distribution for chiplet-based waferscale processors
AssigneeThe Regents of the University of California
InventorsPuneet Gupta, Saptadeep Pal
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Abstract
The present embodiments provide a solution for clock delivery, distribution to an entire waferscale system composed of many chiplets. A clock distribution scheme according to embodiments is also fault tolerant, i.e., the clock distribution network can avoid faulty chiplets on the substrate and reliably distribute clock to all the functional chiplets which are accessible by the network.
Claims13
An apparatus, comprising:
- a plurality of chiplets integrated on a single substrate;
- a clock generation and distribution (ClkDN) mechanism configured to provide a master clock from an external oscillator source to one of the chiplets on the substrate, convert the master clock to a faster clock having a higher frequency than the master clock in the one of the chiplets, and distribute the faster clock from the one of the chiplets to others of the plurality of chiplets across the substrate, wherein the others of the plurality of chiplets are configured to use the distributed faster clock.
A system comprising:
- a wafer comprising an interconnect substrate;
- and
- a plurality of chips incorporated on the wafer, each of the chips comprising one of a processor chip, a memory chip or a networking chip,
- wherein each of the chips includes clock selection and forwarding circuitry configured to:
- receive a master clock and generate a first faster clock that is higher in frequency from the master clock,
- forward the first faster clock to a plurality of neighbor chips, and
- receive a different faster clock from the plurality of neighbor chips.
4 more elements
Dependencies are inferred from the claim text.