Multi-chip high memory bandwidth configuration

A method for fabricating a packaging device, the method comprising:

• providing a first organic laminate substrate and a second organic laminate substrate joined onto a top surface of the first organic laminate substrate, wherein the second organic laminate substrate has a higher wiring density than the first organic laminate substrate;
• bonding a first component device on a top surface of the second organic laminate substrate, the first component device including a fan out wafer level package (FOWLP) and multiple integrated circuits (ICs) that are mounted onto the FOWLP;
• bonding a second component device on a bottom surface of the second organic laminate substrate;
• forming a cavity at the top surface of the first organic laminate substrate;
• and
• mounting the second organic laminate substrate onto the first organic laminate substrate, wherein the second component device is recessed into the cavity of the first organic laminate substrate and has a lower power density than the first component device and is surrounded by the first organic laminate substrate at sidewalls and a bottom of the second component device.

A device comprising:

• an organic laminate substrate;
• a high density interconnect (HDI) on a top surface of the organic laminate substrate;
• a first component device on a top surface of the HDI;
• a second component device on a bottom surface of the HDI, the second component device recesses into a first cavity in the organic laminate substrate;
• and
• a conductive pillar having a first and a second end, the first end being in direct contact with the bottom surface of the HDI and the second end being in direct contact with a bottom surface of the first cavity.